Implemented "legacy" 5x clock divider.

[awygle]

Also allowed adjusting testbench clock divider.

[whitequark]

Hmm it's kind of annoying to have it enabled by default in toolchain tests because that slows them all down and clutters up waveforms. How about driving that signal to 0 early in the testbench, and reverting that in the test for it?

[awygle]

This sounds reasonable but I'm not sure where/how to do that. If I understand right, I don't think I can just .eq() the signal from the testbench because it's set by NextValue in the actual module, and I can't send the command with yield from tb.write in setUp or the constructor either (because those aren't supposed to be generators, maybe?)