Cover P5 connector #10
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Hi Florian, It's a great suggestion. I will look into it. I don't think it will turn out to be simple however, because of the mechanical placement of the P5 header on the Pi. Please see this article: http://raspi.tv/2013/the-leaning-header-of-pi5a-how-best-to-solder-a-header-on-p5 It would be mechanically possible to include a connector for just the even pins of P5, since they have more clearance from P1. However, that doesn't expose all the necessary additional I2C signals for your purposes. I don't know why they placed P5 so close to P1. I understand that it was intended that P5 be populated on the underside of the board, but if it had been moved a few more millimetres it could have been fitted either way. Underside mounting is of course no use for connecting with a Guzunty. |
ghost
assigned 
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I have simply soldered the header this way: And I know many people who have also done it in this way. The only drawback (and that is why there is the solution that you posted) is that you can no longer use ribbon cables to connect e.g. a Gertboard to your Raspberry Pi, but how wants to have a Gertboard when he can have a Guzunty board :-D Furthermore, introducing an additional connector would make no problems for people who do not want to use the P5 header (e.g. because they want to use a Gertboard). In that case the additional header is simply not connected. |
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Oh, thanks for that point. I had assumed there was insufficient space, period. I will include this idea in the next board revision for sure. On a related topic, given your comment about I2C, do you have an I2C interface implemented on the Guzunty? Or were you looking to simply use long pins to pass through the Guzunty board. I ask because I have not yet had time to try an implementation for the I2C interface. Its hardware protocol is rather more complex than SPI and I suspect it might use too many CPLD resources. |
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That sounds very promising, thank you!!
In my case I want to use I2S - the audio interface and not I2C. I want to multiplex the I2S interface, but I don't know if your CPLD is large and fast enough (I have no experience with CPLDs, only with large FPGAs and they had much more capabilities than I ever used). The basic idea is this: There is a master clock of about 12.288 MHz. There are two bitstreams clocked with 3.072 MHz. They have to be merged word-wise into a bitstream clocked with 6.144 MHz. |
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I've raised separate issue #11 to track the I2S requirement. |
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Closing this as the J5 connector was removed in the B+. Pity GPIOs 28 through 31 were not exposed on the new enlarged connector, but that's that. If you want I2S now You'll need to get via the HDMI socket, I think. :( |
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Not completely right, 28 through 31 are no longer accessible, but you can
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Ah, careless me. Yes, you are completely right ;) They are on GPIO's 18 thru 21. Ok but we can still close this issue and keep the I2S one. Are you still interested in a core to do I2S? |
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Yes, you are right, this issue can be closed. Secondly, unfortunately I do
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It would be great to have a CPLD board that also uses the P5 header.
With the current board this header is hidden and can no longer be used (at least from above). Using this header would give a great opportunity to enhance the functionality of the I2S interface.
What do you think about that?
Greetings,
Florian
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