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Fix TS990S SWR read -- strange behavior of RM command reading first R…
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…M turned on for read

New SWR table too for TS990S
#1423
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mdblack98 committed Nov 12, 2023
1 parent 43159e5 commit e7786ce
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Showing 4 changed files with 24 additions and 5 deletions.
9 changes: 9 additions & 0 deletions rigs/kenwood/kenwood.c
Expand Up @@ -1100,6 +1100,15 @@ int kenwood_open(RIG *rig)
// mismatched IDs can still be tested
rig->state.rigport.retry = retry_save;


// TS-990S needs to ensure all RM meters are turned off as first one with read on gets read
// Any RM commands need to be ON/READ/OFF to allow other apps or threads to read meters

if (RIG_IS_TS990S)
{
kenwood_transaction(rig, "RM10;RM20;RM30;RM40;RM50;RM60;", NULL, 0);
}

RETURNFUNC(RIG_OK);
}

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2 changes: 1 addition & 1 deletion rigs/kenwood/kenwood.h
Expand Up @@ -28,7 +28,7 @@
#include "token.h"
#include "idx_builtin.h"

#define BACKEND_VER "20231031"
#define BACKEND_VER "20231112"

#define EOM_KEN ';'
#define EOM_TH '\r'
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10 changes: 6 additions & 4 deletions rigs/kenwood/ts990s.c
Expand Up @@ -59,9 +59,9 @@
#define TS990S_SWR_CAL { 5, \
{ \
{ 0, 1.0f }, \
{ 14, 1.5f }, \
{ 28, 2.0f }, \
{ 42, 3.0f }, \
{ 7, 1.5f }, \
{ 36, 3.0f }, \
{ 43, 6.0f }, \
{ 70, 10.0f } \
} }

Expand Down Expand Up @@ -647,7 +647,9 @@ int ts990s_get_level(RIG *rig, vfo_t vfo, setting_t level, value_t *val)
break;

case RIG_LEVEL_SWR:
retval = kenwood_safe_transaction(rig, "RM21", lvlbuf, sizeof(lvlbuf), 7);
// we need to turn on read, read it, and turn it off again
// first RM meter with read on is the that gets read with RM;
retval = kenwood_safe_transaction(rig, "RM21;RM;RM20", lvlbuf, sizeof(lvlbuf), 8);

if (retval != RIG_OK)
{
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8 changes: 8 additions & 0 deletions src/rig.c
Expand Up @@ -2740,6 +2740,14 @@ int HAMLIB_API rig_get_mode(RIG *rig,
*width = rig->state.cache.widthMainA;
RETURNFUNC(RIG_OK);
}
else if (vfo == RIG_VFO_B)
{
if (rig->state.cache.modeMainB == RIG_MODE_NONE)
{
retcode = caps->get_mode(rig, vfo, mode, width);
return retcode;
}
}

if ((*mode != RIG_MODE_NONE && cache_ms_mode < rig->state.cache.timeout_ms)
&& cache_ms_width < rig->state.cache.timeout_ms)
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