- 👋 Hi, I’m @HimanshuPandey09
- 👀 I’m interested in ... Artificial Neural Networks and VLSI Architecture
- 🌱 I’m currently learning ... Python, Verilog and C
- 💞️ I’m looking to collaborate on ...
- 📫 How to reach me ...pandey.himanshu@outlook.com
Popular repositories Loading
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myProjects
myProjects Public2-bits XOR logic implementation using Single Neuron using Backpropagation
Python 1
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Parameterized-Ripple-Carry-Adder
Parameterized-Ripple-Carry-Adder PublicVerilog Implementation of Parameterized Ripple Carry Adder
Verilog
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Parameterized-Carry-Look-Ahead-Adder
Parameterized-Carry-Look-Ahead-Adder PublicVerilog implementation of Carry Look Ahead Adder
Verilog
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ParameterizedCarryIncrementAdder
ParameterizedCarryIncrementAdder PublicParameterized Verilog implementation of Carry Increment Adder
Verilog
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ParameterizedCarryIncrementAdderwithVariableGroupSize
ParameterizedCarryIncrementAdderwithVariableGroupSize PublicParameterized Verilog implementation for CIA with variable group size given as a parameter.
Verilog
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