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HimanshuPandey09/README.md
  • 👋 Hi, I’m @HimanshuPandey09
  • 👀 I’m interested in ... Artificial Neural Networks and VLSI Architecture
  • 🌱 I’m currently learning ... Python, Verilog and C
  • 💞️ I’m looking to collaborate on ...
  • 📫 How to reach me ...pandey.himanshu@outlook.com

Popular repositories Loading

  1. myProjects myProjects Public

    2-bits XOR logic implementation using Single Neuron using Backpropagation

    Python 1

  2. HimanshuPandey09 HimanshuPandey09 Public

    Config files for my GitHub profile.

  3. Parameterized-Ripple-Carry-Adder Parameterized-Ripple-Carry-Adder Public

    Verilog Implementation of Parameterized Ripple Carry Adder

    Verilog

  4. Parameterized-Carry-Look-Ahead-Adder Parameterized-Carry-Look-Ahead-Adder Public

    Verilog implementation of Carry Look Ahead Adder

    Verilog

  5. ParameterizedCarryIncrementAdder ParameterizedCarryIncrementAdder Public

    Parameterized Verilog implementation of Carry Increment Adder

    Verilog

  6. ParameterizedCarryIncrementAdderwithVariableGroupSize ParameterizedCarryIncrementAdderwithVariableGroupSize Public

    Parameterized Verilog implementation for CIA with variable group size given as a parameter.

    Verilog