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sunxi: display: use VI channel instead of UI channel on DE2
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The DE2 in V3s cannot work well if we use UI channel (channel 1~3, which
is used in the code is 1).

Use VI channel instead (channel 0).

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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Icenowy committed Jan 19, 2017
1 parent abd1033 commit fac813f
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Showing 2 changed files with 19 additions and 15 deletions.
4 changes: 4 additions & 0 deletions arch/arm/include/asm/arch-sunxi/display.h
Original file line number Diff line number Diff line change
Expand Up @@ -458,6 +458,10 @@ struct sunxi_tve_reg {

#define SUNXI_DE2_MUX_GLB_CTL_RT_EN (1 << 0)

#define SUNXI_DE2_VI_CFG_ATTR_EN (1 << 0)
#define SUNXI_DE2_VI_CFG_ATTR_FMT(f) ((f & 0xf) << 8)
#define SUNXI_DE2_VI_CFG_UI_SEL (1 << 15)

#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0)
#define SUNXI_DE2_UI_CFG_ATTR_ALPMOD(m) ((m & 3) << 1)
#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8)
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30 changes: 15 additions & 15 deletions drivers/video/sunxi_display.c
Original file line number Diff line number Diff line change
Expand Up @@ -554,10 +554,9 @@ static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
struct de_bld * const de_bld_regs =
(struct de_bld *)(SUNXI_DE2_MUX0_BASE +
SUNXI_DE2_MUX_BLD_REGS);
struct de_ui * const de_ui_regs =
(struct de_ui *)(SUNXI_DE2_MUX0_BASE +
SUNXI_DE2_MUX_CHAN_REGS +
SUNXI_DE2_MUX_CHAN_SZ * 1);
struct de_vi * const de_vi_regs =
(struct de_vi *)(SUNXI_DE2_MUX0_BASE +
SUNXI_DE2_MUX_CHAN_REGS);
u32 size = SUNXI_DE2_WH(mode->xres, mode->yres);
int channel, i;
u32 data;
Expand All @@ -584,7 +583,7 @@ static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,

writel(0x00000101, &de_bld_regs->fcolor_ctl);

writel(1, &de_bld_regs->route);
writel(0, &de_bld_regs->route);

writel(0, &de_bld_regs->premultiply);
writel(0xff000000, &de_bld_regs->bkcolor);
Expand Down Expand Up @@ -615,16 +614,17 @@ static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_FCC_REGS);
writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_DCSC_REGS);

data = SUNXI_DE2_UI_CFG_ATTR_EN |
SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888) |
SUNXI_DE2_UI_CFG_ATTR_ALPMOD(1) |
SUNXI_DE2_UI_CFG_ATTR_ALPHA(0xff);
writel(data, &de_ui_regs->cfg[0].attr);
writel(size, &de_ui_regs->cfg[0].size);
writel(0, &de_ui_regs->cfg[0].coord);
writel(4 * mode->xres, &de_ui_regs->cfg[0].pitch);
writel(address, &de_ui_regs->cfg[0].top_laddr);
writel(size, &de_ui_regs->ovl_size);
data = SUNXI_DE2_VI_CFG_ATTR_EN |
SUNXI_DE2_VI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888) |
SUNXI_DE2_VI_CFG_UI_SEL;
writel(data, &de_vi_regs->cfg[0].attr);
writel(size, &de_vi_regs->cfg[0].size);
writel(0, &de_vi_regs->cfg[0].coord);
writel(4 * mode->xres, &de_vi_regs->cfg[0].pitch[0]);
writel(0, &de_vi_regs->cfg[0].pitch[1]);
writel(0, &de_vi_regs->cfg[0].pitch[2]);
writel(address, &de_vi_regs->cfg[0].top_laddr[0]);
writel(size, &de_vi_regs->ovl_size[0]);
}

static void sunxi_composer_enable(void)
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