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This project is a RISC-V simulator implemented in C,C++,Python, designed to execute RISC-V instructions and provide a simulated environment for testing and development of RISC-V programs. It includes support for a subset of the RISC-V instruction set, memory management, and system calls

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Functional Simulator for RISC-V

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README

Table of contents


Directory Structure:

CS204-Project
    ├─ Phase 3
         ├─ Src
            ├─ Backend
                ├─ Headers
                    └─ Cache.h
                    ├─ Common.h
                    ├─ Decode.h
                    ├─ Execute.h
                    ├─ Fetch.h
                    ├─ MeMAccess.h
                    ├─ Pipeline.h
                    ├─ Predictor.h
                    └─ Writeback.h
                    ├─ Hazard.h
                ├─ clock.txt
                ├─ debug.cpp
                ├─ inst.mc
                ├─ main.cpp
                ├─ memory.txt
                ├─ output.txt
                ├─ register.txt
                └─ test.cpp
            ├─ Frontend
                ├─ pycache
                ├─ clock.txt
                ├─ functions.py
                ├─ gui_main.py
                ├─ hazard.txt
                ├─ memory.txt
                ├─ output.txt
                ├─ register.txt
                └─ stages.txt
         ├─ doc
            ├─ design-doc.docx
         ├─ test
            ├─ bubblesort.mc
            ├─ compare.mc
            ├─ fib.mc
            ├─ fibonacci.mc
            ├─ search.mc
            ├─ simple_add.mc
            ├─ sum_of_array.mc
            ├─ test.mc
            └─ test.txt
         └─ Readme.md
    └─ .gitignore


How to Execute

For running programme:
First, make sure stteamlit library is installed for python GUI. \

$pip install streamlit

Then, open terminal and run following instructions:

$cd Phase 3
$cd src
$cd Backend
$streamlit run gui_main.py

You will get your desired output on the GUI.


Authors

  1. ABHISHEK JAISWAL (2021csb1061@iitrpr.ac.in)
  2. AJAYBEER SINGH (2021csb1063@iitrpr.ac.in)
  3. AKANKSH CAIMI (2021csb1064@iitrpr.ac.in)
  4. DEVANSHU DHAWAN (2021csb1082@iitrpr.ac.in)

About

This project is a RISC-V simulator implemented in C,C++,Python, designed to execute RISC-V instructions and provide a simulated environment for testing and development of RISC-V programs. It includes support for a subset of the RISC-V instruction set, memory management, and system calls

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