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verilog-logic-circuit-project

Ferdowsi University of Mashhad Logic Circuit Lock

designing a Semi-mechanical Lock with verilog language

Table of Contents
  1. About The Project
  2. Getting Started
  3. Usage
  4. Roadmap
  5. Contributing
  6. License
  7. Contact
  8. Acknowledgments

About The Project

Built With

Technologies and Tools Utilized in this Project

  • Verilog

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Contributing

Contributions are what make the open source community such an amazing place to learn, inspire, and create. Any contributions you make are greatly appreciated.

If you have a suggestion that would make this better, please fork the repo and create a pull request. You can also simply open an issue with the tag "enhancement". Don't forget to give the project a star! Thanks again!

  1. Fork the Project
  2. Create your Feature Branch (git checkout -b feature/AmazingFeature)
  3. Commit your Changes (git commit -m 'Add some AmazingFeature')
  4. Push to the Branch (git push origin feature/AmazingFeature)
  5. Open a Pull Request

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License

Distributed under the MIT License. See LICENSE for more information.

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Contact

Javid Chaji

X

javid.chaji@gmail.com

Project Link: https://github.com/JavidChaji/FUM-Logic-Circuit-Lock

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Acknowledgments

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Releases

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Packages

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