Upstream several Intel extensions #176

MrSidims · 2020-11-05T10:47:05Z

No description provided.

MrSidims · 2020-11-16T11:57:49Z

@bashbaug @mkinsner @johnkslang could you please take a look?

MrSidims · 2020-12-14T20:23:15Z

@mkinsner @bashbaug could you please take a look and possibly merge? It looks like misalignment between SPIR-V headers starts bringing and attention: intel/llvm#2889

New spirv.hpp is generated from github.com/KhronosGroup/SPIRV-Headers using following PRs: - KhronosGroup/SPIRV-Headers#176 - KhronosGroup/SPIRV-Headers#177 with an exception of `SPV_INTEL_fpga_loop_fuse` and `SPV_INTEL_long_constant_composite` extensions definitions that were added manually in this PR.

dneto0

So far this change looks ok.
For one thing, I verified that all the enum values are placed in the right order.

I'll need to prepare a patch for SPIRV-Tools to support the new enumerant kinds FPDenorm_Mode and FPOperation_Mode

include/spirv/unified1/spirv.core.grammar.json

dneto0 · 2021-01-19T22:49:33Z

include/spirv/unified1/spirv.core.grammar.json

@@ -9088,6 +9333,34 @@
        }
      ]
    },
+    {
+      "category" : "ValueEnum",
+      "kind" : "FPDenormMode",


Adding a new operand kind like this will break the SPIRV-Tools build.
I plan to prepare a patch to SPIRV-Tools to absorb this change.

This is the kind of error I get when rebasing this change against master and rebuilding SPIRV-Tools:

In file included from ...spirv-tools/source/operand.cpp:36:
third_party/spirv-tools/operand.kinds-unified1.inc:703:172: error: ‘SPV_OPERAND_TYPE_FPDENORM_MODE’ was not declared in this scope; did you mean ‘SPV_OPERAND_TYPE_MEMORY_MODEL’?
703 | {"FunctionDenormModeINTEL", 5823, 1, pygen_variable_caps_FunctionFloatControlINTEL, 1, pygen_variable_exts_SPV_INTEL_float_controls2, {SPV_OPERAND_TYPE_LITERAL_INTEGER, SPV_OPERAND_TYPE_FPDENORM_MODE}, 0xffffffffu, 0xffffffffu},
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| SPV_OPERAND_TYPE_MEMORY_MODEL
third_party/spirv-tools/operand.kinds-unified1.inc:724:179: error: ‘SPV_OPERAND_TYPE_FPOPERATION_MODE’ was not declared in this scope; did you mean ‘SPV_OPERAND_TYPE_EXECUTION_MODE’?
724 | {"FunctionFloatingPointModeINTEL", 6080, 1, pygen_variable_caps_FunctionFloatControlINTEL, 1, pygen_variable_exts_SPV_INTEL_float_controls2, {SPV_OPERAND_TYPE_LITERAL_INTEGER, SPV_OPERAND_TYPE_FPOPERATION_MODE}, 0xffffffffu, 0xffffffffu},
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| SPV_OPERAND_TYPE_EXECUTION_MODE
third_party/spirv-tools/operand.kinds-unified1.inc:1229:4: error: ‘SPV_OPERAND_TYPE_FPDENORM_MODE’ was not declared in this scope; did you mean ‘SPV_OPERAND_TYPE_MEMORY_MODEL’?
1229 | {SPV_OPERAND_TYPE_FPDENORM_MODE, ARRAY_SIZE(pygen_variable_FPDenormModeEntries), pygen_variable_FPDenormModeEntries},
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| SPV_OPERAND_TYPE_MEMORY_MODEL
third_party/spirv-tools/operand.kinds-unified1.inc:1230:4: error: ‘SPV_OPERAND_TYPE_FPOPERATION_MODE’ was not declared in this scope; did you mean ‘SPV_OPERAND_TYPE_EXECUTION_MODE’?
1230 | {SPV_OPERAND_TYPE_FPOPERATION_MODE, ARRAY_SIZE(pygen_variable_FPOperationModeEntries), pygen_variable_FPOperationModeEntries},
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| SPV_OPERAND_TYPE_EXECUTION_MODE

I have a pending patch for SPIRV-Tools. KhronosGroup/SPIRV-Tools#4116
That will have to land before this patch (to prevent the SPIRV-Tools build from breaking).

Yeah, it also required changes in the headers builder itself.

I've landed the SPIRV-Tools change, so we're clear to land this one, from my perspective.

dneto0 · 2021-01-19T22:51:21Z

Please rebase this change against master, to keep it fresh.

dneto0 · 2021-01-19T23:04:50Z

include/spirv/unified1/spirv.core.grammar.json

+        { "kind" : "LiteralString", "name" : "'Asm target'" }
+      ],
+      "capabilities" : [ "AsmINTEL" ],
+      "extensions" : [ "SPV_INTEL_inline_assembly" ],


I think the guidance is that the new capability enums have an "extensions" list. In turn, the instructions and non-capability enumerants are guarded by a new capability. I find it more clear that way.

Just to clarify, the suggestion is to remove extensions list from codes' definitions, right?

Yes, for everything that isn't a capability.
The capability should keep it.

dneto0 · 2021-01-19T23:07:57Z

include/spirv/unified1/spirv.core.grammar.json

+          "enumerant" : "AllowContractFastINTEL",
+          "value" : "0x10000",
+          "capabilities" : [ "FPFastMathModeINTEL" ],
+          "extensions" : [ "SPV_INTEL_fp_fast_math_mode" ]


I think this and the next entry should have version set to "None"

Thanks! Missed that one.

dneto0 · 2021-01-20T01:55:10Z

include/spirv/unified1/spirv.core.grammar.json

+      "enumerants" : [
+        {
+          "enumerant" : "Preserve",
+          "value" : 0


I think it is preferable to add:

"capabilities" : [ "FunctionFloatControlINTEL" ], "version" : "None"

Thanks! It wasn't mentioned in the spec, but I guess you are right, I'll open a spec issue.

dneto0 · 2021-01-20T01:55:38Z

include/spirv/unified1/spirv.core.grammar.json

+      "kind" : "FPOperationMode",
+      "enumerants" : [
+        {
+          "enumerant" : "IEEE",


Similarly, I think it's preferable to add:

"capabilities" : [ "FunctionFloatControlINTEL" ], "version" : "None"

This patch supports new Intel extensions added via KhronosGroup/SPIRV-Headers#176 SPV_INTEL_fooat_controls2 requires extra support to add two new operand types: SPV_OPERAND_TYPE_FPDENORM_MODE SPV_OPERAND_TYPE_FPOPERATION_MODE

raunraun · 2021-01-20T02:16:39Z

Will merge when SPIRV-Tiils#4116 is given the OK by the bots.

Spec: https://github.com/intel/llvm/blob/2237b42035f31cb10b16d4f9abaeed45bed98587/sycl/doc/extensions/SPIRV/SPV_INTEL_fpga_buffer_location.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_inline_assembly.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_int.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_usm_storage_classes.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_variable_length_array.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_io_pipes.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_accesses.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Spec: https://github.com/intel/llvm/blob/e185a6b49e4bc9806a799b774977f1196b24f0d6/sycl/doc/extensions/SPIRV/SPV_INTEL_vector_compute.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Spec: https://github.com/intel/llvm/blob/39fa9b0cbfbae88327118990a05c5b387b56d2ef/sycl/doc/extensions/SPIRV/SPV_INTEL_float_controls2.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fpga_cluster_attributes.asciidoc https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fp_fast_math_mode.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

MrSidims · 2021-01-20T11:43:21Z

Shall I squash commits before merging to eliminate the last "Apply suggestions" commit?

This patch supports new Intel extensions added via KhronosGroup/SPIRV-Headers#176 SPV_INTEL_fooat_controls2 requires extra support to add two new operand types: SPV_OPERAND_TYPE_FPDENORM_MODE SPV_OPERAND_TYPE_FPOPERATION_MODE

dneto0 · 2021-01-20T14:58:49Z

Shall I squash commits before merging to eliminate the last "Apply suggestions" commit?

I don't think it's necessary to squash.

dneto0

Looks good to me.
I've checked this with the corresponding SPIRV-Tools change, and the combination works together.
Thanks!

MrSidims · 2021-01-20T15:04:31Z

Looks good to me.
I've checked this with the corresponding SPIRV-Tools change, and the combination works together.
Thanks!

Good news! Thanks for making the things going!

New spirv.hpp is generated from github.com/KhronosGroup/SPIRV-Headers using following PRs: - KhronosGroup/SPIRV-Headers#176 - KhronosGroup/SPIRV-Headers#177 with an exception of `SPV_INTEL_fpga_loop_fuse` and `SPV_INTEL_long_constant_composite` extensions definitions that were added manually in this PR.

MrSidims mentioned this pull request Nov 6, 2020

Update spirv.hpp KhronosGroup/SPIRV-LLVM-Translator#810

Merged

MrSidims force-pushed the private/MrSidims/OtherExtensions branch from 01f0fd1 to fb44893 Compare November 10, 2020 09:07

MrSidims mentioned this pull request Nov 16, 2020

Manage SPIR-V headers as an external dependency KhronosGroup/SPIRV-LLVM-Translator#210

Closed

MrSidims mentioned this pull request Nov 30, 2020

Add support for SPV_INTEL_fp_fast_math_mode KhronosGroup/SPIRV-LLVM-Translator#822

Merged

MrSidims mentioned this pull request Dec 14, 2020

How to emit SPIRV and how to emit LLVM? intel/llvm#2889

Closed

MrSidims force-pushed the private/MrSidims/OtherExtensions branch from 9eac30d to 0233c78 Compare December 16, 2020 16:36

dneto0 reviewed Jan 19, 2021

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dneto0 reviewed Jan 20, 2021

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dneto0 mentioned this pull request Jan 20, 2021

Support pending Intel extensions KhronosGroup/SPIRV-Tools#4116

Merged

MrSidims added 14 commits January 20, 2021 13:14

Upstream SPV_INTEL_fpga_buffer_location extension

d5035de

Spec: https://github.com/intel/llvm/blob/2237b42035f31cb10b16d4f9abaeed45bed98587/sycl/doc/extensions/SPIRV/SPV_INTEL_fpga_buffer_location.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_inline_assembly extension

7669e05

Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_inline_assembly.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_arbitrary_precision_integers extensions

a001134

Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_int.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_usm_storage_classes extension

e202eb8

Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_usm_storage_classes.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_variable_length_array extension

ef87dd1

Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_variable_length_array.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_io_pipes extension

0e75681

Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_io_pipes.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_fpga_memory_accesses extension

2b76471

Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_accesses.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_vector_compute extension

24e9c63

Spec: https://github.com/intel/llvm/blob/e185a6b49e4bc9806a799b774977f1196b24f0d6/sycl/doc/extensions/SPIRV/SPV_INTEL_vector_compute.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_float_controls2 extension

ea79113

Spec: https://github.com/intel/llvm/blob/39fa9b0cbfbae88327118990a05c5b387b56d2ef/sycl/doc/extensions/SPIRV/SPV_INTEL_float_controls2.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update SPV_INTEL_function_pointers extension

0c29056

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update SPV_INTEL_kernel_attributes extension

ad00ca3

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update SPV_INTEL_fpga_loop_controls extension

b6be746

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Add SPV_INTEL_loop_fuse extension

8987518

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

MrSidims added 3 commits January 20, 2021 13:14

Add SPV_INTEL_long_constant_composite extension

f9797ef

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update generated files

b690b3e

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Apply suggestions to Intel extensions PR

0dd29fb

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

MrSidims force-pushed the private/MrSidims/OtherExtensions branch from 0233c78 to 0dd29fb Compare January 20, 2021 11:38

dneto0 approved these changes Jan 20, 2021

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johnkslang self-requested a review January 20, 2021 16:38

johnkslang merged commit 8bb2420 into KhronosGroup:master Jan 20, 2021

AlexeySachkov mentioned this pull request Jan 10, 2022

[SPIR-V] Add SPV_INTEL_long_composites intel/llvm#2848

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Upstream several Intel extensions #176

Upstream several Intel extensions #176

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Upstream several Intel extensions #176

Upstream several Intel extensions #176

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