Merge pull request #608 from endofexclusive/cdcvf2505

Added Texas Instruments CDCVF2505 PLL clock driver

Timer_PLL.dcm

@@ -13,15 +13,21 @@ F http://www.analog.com/media/en/technical-documentation/data-sheets/ADF4002.pdf
 $ENDCMP
 #
 $CMP ADF4350
-D 137.5-4400MHz fractional-N PLL, LFCSP-32 
+D 137.5-4400MHz fractional-N PLL, LFCSP-32
 K fractional-N PLL
 F http://www.analog.com/media/en/technical-documentation/data-sheets/ADF4350.pdf
 $ENDCMP
 #
 $CMP ADF4351
-D 35-4400MHz fractional-N PLL, LFCSP-32 
+D 35-4400MHz fractional-N PLL, LFCSP-32
 K fractional-N PLL
 F http://www.analog.com/media/en/technical-documentation/data-sheets/ADF4351.pdf
 $ENDCMP
 #
+$CMP CDCVF2505
+D Clock Phase-Lock Loop Clock Driver, 24-200MHz, 3.3V, SOIC-8/TSSOP-8
+K pll clock driver
+F http://www.ti.com/lit/ds/symlink/cdcvf2505.pdf
+$ENDCMP
+#
 #End Doc Library

Timer_PLL.lib

@@ -1,4 +1,4 @@
-EESchema-LIBRARY Version 2.3
+EESchema-LIBRARY Version 2.4
 #encoding utf-8
 #
 # ADF4002BCPZ
@@ -82,38 +82,62 @@ $ENDFPLIST
 DRAW
 S 700 1000 -700 -1000 0 1 10 f
 X CLK 1 -800 600 100 R 50 50 1 1 I
-X DATA 2 -800 500 100 R 50 50 1 1 I
-X LE 3 -800 400 100 R 50 50 1 1 I
-X CE 4 -800 200 100 R 50 50 1 1 I
-X SW 5 800 -800 100 L 50 50 1 1 I
-X Vp 6 -400 1100 100 D 50 50 1 1 W
-X CPout 7 800 -600 100 L 50 50 1 1 I
-X CPGND 8 -400 -1100 100 U 50 50 1 1 W
-X AGND 9 -300 -1100 100 U 50 50 1 1 W
 X AVDD 10 -300 1100 100 D 50 50 1 1 W
-X VTUNE 20 800 -500 100 L 50 50 1 1 I
-X MUXOUT 30 800 600 100 L 50 50 1 1 O
 X AGNDVCO 11 -200 -1100 100 U 50 50 1 1 W
-X AGNDVCO 21 0 -1100 100 U 50 50 1 1 W
-X SDGND 31 200 -1100 100 U 50 50 1 1 W
 X RF_OUT_A+ 12 800 300 100 L 50 50 1 1 O
-X RSET 22 -800 -600 100 R 50 50 1 1 I
-X SDVDD 32 300 1100 100 D 50 50 1 1 W
 X RF_OUT_A- 13 800 200 100 L 50 50 1 1 O
-X VCOM 23 -800 -400 100 R 50 50 1 1 I
-X EP 33 300 -1100 100 U 50 50 1 1 W
 X RF_OUT_B+ 14 800 -100 100 L 50 50 1 1 O
-X VREF 24 -800 -500 100 R 50 50 1 1 I
 X RF_OUT_B- 15 800 -200 100 L 50 50 1 1 O
-X LD 25 800 700 100 L 50 50 1 1 I
 X VVCO 16 -100 1100 100 D 50 50 1 1 W
-X PDB_RF 26 -800 100 100 R 50 50 1 1 I
 X VVCO 17 0 1100 100 D 50 50 1 1 W
-X DGND 27 100 -1100 100 U 50 50 1 1 W
 X AGNDVCO 18 -100 -1100 100 U 50 50 1 1 W
-X DVDD 28 100 1100 100 D 50 50 1 1 W
 X TEMP 19 -800 -300 100 R 50 50 1 1 I
+X DATA 2 -800 500 100 R 50 50 1 1 I
+X VTUNE 20 800 -500 100 L 50 50 1 1 I
+X AGNDVCO 21 0 -1100 100 U 50 50 1 1 W
+X RSET 22 -800 -600 100 R 50 50 1 1 I
+X VCOM 23 -800 -400 100 R 50 50 1 1 I
+X VREF 24 -800 -500 100 R 50 50 1 1 I
+X LD 25 800 700 100 L 50 50 1 1 I
+X PDB_RF 26 -800 100 100 R 50 50 1 1 I
+X DGND 27 100 -1100 100 U 50 50 1 1 W
+X DVDD 28 100 1100 100 D 50 50 1 1 W
 X REFIN 29 -800 -100 100 R 50 50 1 1 I
+X LE 3 -800 400 100 R 50 50 1 1 I
+X MUXOUT 30 800 600 100 L 50 50 1 1 O
+X SDGND 31 200 -1100 100 U 50 50 1 1 W
+X SDVDD 32 300 1100 100 D 50 50 1 1 W
+X EP 33 300 -1100 100 U 50 50 1 1 W
+X CE 4 -800 200 100 R 50 50 1 1 I
+X SW 5 800 -800 100 L 50 50 1 1 I
+X Vp 6 -400 1100 100 D 50 50 1 1 W
+X CPout 7 800 -600 100 L 50 50 1 1 I
+X CPGND 8 -400 -1100 100 U 50 50 1 1 W
+X AGND 9 -300 -1100 100 U 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# CDCVF2505
+#
+DEF CDCVF2505 U 0 20 Y Y 1 F N
+F0 "U" -350 350 50 H V C CNN
+F1 "CDCVF2505" 400 350 50 H V C CNN
+F2 "" -400 300 50 H I C CNN
+F3 "" -400 300 50 H I C CNN
+$FPLIST
+ SOIC*3.9x4.9mm*P1.27mm*
+ TSSOP*4.4x3mm*P0.65mm*
+$ENDFPLIST
+DRAW
+S -400 300 400 -300 0 1 10 f
+X CLKIN 1 -500 0 100 R 50 50 1 1 I
+X 1Y1 2 500 0 100 L 50 50 1 1 T
+X 1Y0 3 500 100 100 L 50 50 1 1 T
+X GND 4 0 -400 100 U 50 50 1 1 W
+X 1Y2 5 500 -200 100 L 50 50 1 1 T
+X VDD 6 0 400 100 D 50 50 1 1 W
+X 1Y3 7 500 -100 100 L 50 50 1 1 T
+X CLKOUT 8 500 200 100 L 50 50 1 1 T
 ENDDRAW
 ENDDEF
 #