Added Texas Instruments CDCVF2505 PLL clock driver #608
Conversation
The part is available in SOIC-8 and TSSOP-8 with the same pinout. NOTE: checklib.py says CDCVF2505:CLKOUT violates KLC S4.4. However, this is a 3-state output according to the datasheet functional block diagram.
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Thanks for contributing to KiCad! It's because of a willing community like you that the library can grow and improve. You will find a lost of rules and guidelines for the KiCad library at http://kicad-pcb.org/libraries/klc/. Please see that webpage for more information about the review items below. This is an excellent symbol! Great first contribution!
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Description updated according to recommendation: "Clock Phase-Lock Loop Clock Driver, 24-200MHz, 3.3V, SOIC-8/TSSOP-8" refdes at top left, name at top right
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Sure. The position policy for refdes and name was not fully clear from the KLC illustrations. Here is a second try. :-) |
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Thanks! That text position is one of many things that KLC isn't clear about, but we strive to address issues as they come up. I hope to see more contributions from you in the future! By the way, your color scheme above is quite a departure from the default KiCad look. |
Datasheet:
http://www.ti.com/lit/ds/symlink/cdcvf2505.pdf
NOTE: CLKOUT and 1Y* are 3-state outputs according to the datasheet functional block diagram.