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If your screenshoot of the symbol also include the pin type It is easier to review |
Because of all the fixes above, please post another screenshot of the symbol when you're done. Lastly, and this is not required, would you be willing to make the other parts in this family? |
In fact, Cypress does not provide guidelines for their packages. I've prepared a TI-compatible footprint, which seems to fit to dimenstions of CY768 MCU. |
Even just adding the SSOP is great. That was no requirement but adding the 13/14/15/16 or any other packages is nice. Thank you!
Please post a screenshot of both symbols for ease of review. Thank you. |
The footprint from TI should be fine, both vendors' QFN56 has exactly the same ep dimensions. However, ADI uses an exact EP dimensions for EP pad in their LFCSP, but that's rather an exception than a rule. EP is recommended to be soldered to ground, but not necessarily. I've moved it away to leave a choice. I've also moved CLKOUT to the right, but I disagree to move anything else. All pins on right are creating a consistent FIFO interface to FPGA, and having such pins on both sides will make a mess on a schematic. Updated with ALIAS to 14A as well and fixed keywords. |
Thank you for all the changes!
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Thanks for all comments, I hope everything is OK now. As for the EP, I've read it somewhere, but not in a datasheet for sure. It might have been PCB layout guide or reference design docs... Generally speaking, for best thermal management, pad "can" be soldered to a solid ground plane with a bunch of vias all over it. But I admit, the source of this revelations is suspicious for me either, so it's better to leave the pin to let the user to decide what to do with it. |
Description and keywords are OK now. And it's best to leave the pad separate, unless we find a reference for the connection, as you've done and for the reason you state. Thank you! |
There are a few issues with this symbol.
@evanshultz Questions:
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@whitequark There's a lot here. Let me respond one-by-one. Issues:
Answers:
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@evanshultz Thanks for such a quick and thorough reply! For the project I'm currently working on, I took a decision to get every footprint upstream in KiCAD libraries, and I am very happy with it.
It's on Figure 41: "Via hole for thermally connecting the QFN to the circuit board ground plane", plus "The QFN metal die paddle must be soldered to the PCB's thermal pad" in the paragraph of text above, which are unambiguous in my opinion. Regarding the footprint with the thermal vias, should it be a generic variant of the footprint? Or do you think it should be done as a Cypress-prefixed variant? |
Yeah, now that you put that all together it does seem to indicate it must be connected to ground. Still rather ambiguous compared with most datasheets. If you don't mind, let's give Cypress a day or two to respond and then decide. |
Sounds good. Cypress is extremely thorough in documenting the software side of their microcontrollers but it seems that mechanical side is lacking for some reason. |
@evanshultz It's been 9 days--any answer from Cypress? We made a footprint, anyway, do you want me to submit that? |
Thanks for pinging me on this topic! Unfortunately I have not gotten anything useful back. I have raised this issue through another avenue. Let's give it a couple days and hope this approach works better. |
@whitequark I'm told the CY8CKIT-50 design is the best reference design from Cypress, but it has only a few randomly-located vias in the thermal pad and it also has a single square paste pad half the edge side of the copper pad. They said a 5x5 via pattern would be better but with only a ~6mm thermal pad a single paste pad is best. But since KiCad typically uses smaller paste pads and it's also in AN72845 we'll do it. So all together, here is the best info I've gathered about the footprint (note that I've rounded things since we work in mm but the Cypress designs are all in mils):
What are the parameters of your footprint? Sorry this took so long. Thanks for bringing it up. |
Hi! I think most of these parameters are totally reasonable (although the thermal pad does seem a bit large to me, but never mind). I did run into a couple of things however. First, to get the via cap, I had to get creative with the artwork as you can see here: This is because the plane is negative and we want mask to be removed everywhere but over the vias. There's nothing wrong with this exactly but it is odd (and Kicad should probably support this butter but never mind). Second, I'm not a big fan of the proposed stencil layer (seen here): Specifically, having paste over top of vias is something I typically try to avoid. Our footprint went a different way: This gave us 55% paste coverage without being over the top of the vias (actually this image is slightly wrong because of other changes but you can see the idea), and we could easily get to 70% with this technique. That said, I'm open to doing it either way, just let me know what you'd like to go with. I'll submit a new footprint PR, then a symbol PR updating this symbol to point to the new footprint. Sound good? |
I'm fine with a modified paste layout. There are many ways to get there. :) I understand what you mean by keeping the mask over vias to avoid paste drainage. Since Cypress calls out mask over vias in the datasheet I'm OK with it here. We default to no mask over vias, so please make this a Cypress-specific footprint if it's customized. |
CY7C68013A-56LTX
FX2LP 8-bit USB MCU QFN-56
CY7C68013A, MCU, USB
http://www.cypress.com/file/138911/download
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