UART_Implementation

VHDL Implementation

An Implementation of UART protocol in VHDL

Multiple Baud rate
- Two baud rate option given 9600 Baud and 115200 Baud
- Baud_rate count is derived based on system clock of 12MHz.
The Final block consisit of a loopback where the Transmitter is connected with the receiver.

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
PISO.vhd		PISO.vhd
READ.md		READ.md
README.md		README.md
RX.vhd		RX.vhd
RXCntrl.vhd		RXCntrl.vhd
RX_Cntrl.vhd		RX_Cntrl.vhd
TX.vhd		TX.vhd
TxCntrll.vhd		TxCntrll.vhd
UART.mpf		UART.mpf
UART_Demo.vhd		UART_Demo.vhd
baud_gen.vhd		baud_gen.vhd

Provide feedback