Name		Name	Last commit message	Last commit date
Latest commit History 141 Commits
0. Getting Started.v		0. Getting Started.v
1. Output Zero.v		1. Output Zero.v
100. Decade counter again.v		100. Decade counter again.v
101. Slow decade counter.v		101. Slow decade counter.v
102. counter 1-12.v		102. counter 1-12.v
103. counter 1000.v		103. counter 1000.v
104. 4-digit decimal counter.v		104. 4-digit decimal counter.v
105. 12-hour clock.v		105. 12-hour clock.v
106. 4-bit shift register.v		106. 4-bit shift register.v
107. Left or right rotator.v		107. Left or right rotator.v
108. left\right arithmetic shift by 1 or 8.v		108. left\right arithmetic shift by 1 or 8.v
109. 5-bit LFSR.v		109. 5-bit LFSR.v
110. 3-bit LFSR.v		110. 3-bit LFSR.v
111. 32-bit LFSR.v		111. 32-bit LFSR.v
112. Shift register.v		112. Shift register.v
113. Shift register.v		113. Shift register.v
114. 3-input LUT.v		114. 3-input LUT.v
115.v		115.v
116.v		116.v
117.v		117.v
118. Simple FSM 1 (asynchronous reset).v		118. Simple FSM 1 (asynchronous reset).v
119. Simple FSM 1 (synchronous reset).v		119. Simple FSM 1 (synchronous reset).v
120. Simple FSM 2 (synchronous reset).v		120. Simple FSM 2 (synchronous reset).v
121. Simple FSM 2 (synchronous reset).v		121. Simple FSM 2 (synchronous reset).v
122. Simple state transitions 3.v		122. Simple state transitions 3.v
123. Simple one-hot state transitions 3.v		123. Simple one-hot state transitions 3.v
124. Simple FSM 3 (asynchronous reset).v		124. Simple FSM 3 (asynchronous reset).v
125. Simple FSM3 (synchronous reset).v		125. Simple FSM3 (synchronous reset).v
126.Design a Moore FSM.v		126.Design a Moore FSM.v
127. Lemmings 1.v		127. Lemmings 1.v
128. Lemmings 2.v		128. Lemmings 2.v
129. Lemmings 3.v		129. Lemmings 3.v
130. Lemmings 4.v		130. Lemmings 4.v
131. One-hot FSM.v		131. One-hot FSM.v
132. PS\2 packet parser.v		132. PS\2 packet parser.v
133. PS\2 packet parser and datapath.v		133. PS\2 packet parser and datapath.v
134. Serial receiver.v		134. Serial receiver.v
2. Simple wire.v		2. Simple wire.v
3. Four wires.v		3. Four wires.v
4. Inverter.v		4. Inverter.v
45. NOR.v		45. NOR.v
46. Another gate.v		46. Another gate.v
47. Two gates.v		47. Two gates.v
48. More logic gates.v		48. More logic gates.v
49. 7420 chip.v		49. 7420 chip.v
5. AND gate.v		5. AND gate.v
50. Truth tables.v		50. Truth tables.v
51. Two-bit equality.v		51. Two-bit equality.v
52. Simple circuit A .v		52. Simple circuit A .v
53. Mt2015 q4b. v		53. Mt2015 q4b. v
53. Simple circuit B.v		53. Simple circuit B.v
54. Combine circuits A and B.v		54. Combine circuits A and B.v
55. Ring or vibrate.v		55. Ring or vibrate.v
56. Thermostat.v		56. Thermostat.v
57. 3-bit population count.v		57. 3-bit population count.v
58. Gates and vectors.v		58. Gates and vectors.v
59. Even longer vectors.v		59. Even longer vectors.v
60. 2-to-1 multiplexer.v		60. 2-to-1 multiplexer.v
61. 2-to-1 bus multiplexer.v		61. 2-to-1 bus multiplexer.v
62. 9-to-1 multiplexer.v		62. 9-to-1 multiplexer.v
63. 256-to-1 multiplexer.v		63. 256-to-1 multiplexer.v
64. 256-to-1 4-bit multiplexer.v		64. 256-to-1 4-bit multiplexer.v
65. Half adder.v		65. Half adder.v
66. Full adder.v		66. Full adder.v
67. 3-bit binary adder.v		67. 3-bit binary adder.v
68. Adder.v		68. Adder.v
69. Signed addition overflow.v		69. Signed addition overflow.v
70. 100-bit binary adder.v		70. 100-bit binary adder.v
71. 4-digit BCD adder.v		71. 4-digit BCD adder.v
72. 3-variable.v		72. 3-variable.v
73. 4-variable.v		73. 4-variable.v
74. 4-variable.v		74. 4-variable.v
75. 4-variable.v		75. 4-variable.v
76. Minimum SOP and POS.v		76. Minimum SOP and POS.v
77. Karnaugh map.v		77. Karnaugh map.v
78. Karnaugh map.v		78. Karnaugh map.v
79. K-map implemented with a multiplexer.v		79. K-map implemented with a multiplexer.v
80. D flip-flop.v		80. D flip-flop.v
81. D flip-flops.v		81. D flip-flops.v
82. DFF with reset.v		82. DFF with reset.v
83. DFF with reset value.v		83. DFF with reset value.v
84. DFF with asynchronous reset.v		84. DFF with asynchronous reset.v
85. DFF with byte enable.v		85. DFF with byte enable.v
86. D latch.v		86. D latch.v
87. DFF.v		87. DFF.v
88. DFF.v		88. DFF.v
89. DFF+gate.v		89. DFF+gate.v
90. Mux and DFF.v		90. Mux and DFF.v
91. Mux and DFF.v		91. Mux and DFF.v
92. DFFs and gates.v		92. DFFs and gates.v
93. Create circuit from truth table.v		93. Create circuit from truth table.v
94. Detect an edge.v		94. Detect an edge.v
95. Detect both edge.v		95. Detect both edge.v
96. Edge capture register.v		96. Edge capture register.v
97. Dual-edge triggered filp-flop.v		97. Dual-edge triggered filp-flop.v
98. Four-bit binary counter.v		98. Four-bit binary counter.v
99. Decade counter.v		99. Decade counter.v
Alwaysblock1.v		Alwaysblock1.v
How to avoid lathes?		How to avoid lathes?
If statement latches.v		If statement latches.v

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