fast_divide.vhdl: Optimize division #759
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Benchamrking shows that average latency per division is reduced from 13 clock cycles to 8 clock cycles.
This may be a bug in Vivado. At least, the previous version worked fine with the GHDL simulator. I'm guessing Vivado has a problem with the "variable length" assignment. The fix introduced here ensures that all 32 bits are assigned always.
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Interestingly, the utilization report says that the number of registers is reduced (from 241 to 180), but the number of LUTs is increased (from 648 to 670). Not a huge difference. |
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The average latency is reduced from 13 clock cycles to 8 clock cycles.
The reduction is achieved by performing the initial normalization in one clock cycle, rather than in five clock cycles. Furthermore, one additional clock cycle at end of calculation is removed (state "preoutput").