Fix issue 118

CORE/vhdl/main.vhd

@@ -369,6 +369,9 @@ architecture synthesis of main is
    signal hard_reset_n_d       : std_logic := '1';
    signal cold_start_done      : std_logic := '0';
 
+   constant C_RESET_CORE_DELAY : natural := 320_000; -- cirka 10 milliseconds
+   signal reset_core_delay     : natural range 0 to C_RESET_CORE_DELAY := 0;
+
    -- Core's simulated expansion port
    signal core_roml            : std_logic;
    signal core_romh            : std_logic;
@@ -558,11 +561,24 @@ begin
       -- as reset_core_int_n = '0' so we need to ignore cart_reset_i in this case
       if reset_core_int_n = '0' then
          reset_core_n <= '0';
+      elsif reset_core_delay > 0 then
+         reset_core_n <= '0';
       elsif cart_reset_i = '0' and prevent_reset = '0' then
          reset_core_n <= '0';
       end if;
    end process;
 
+   core_delay_proc : process (clk_main_i)
+   begin
+      if rising_edge(clk_main_i) then
+         if reset_core_int_n = '0' then
+            reset_core_delay <= C_RESET_CORE_DELAY;
+         elsif reset_core_delay > 0 then
+            reset_core_delay <= reset_core_delay - 1;
+         end if;
+      end if;
+   end process core_delay_proc;
+
    -- To make sure that cartridges in the Expansion Port start properly, we must not do a hard reset and mask the $8000 memory area,
    -- when the core is launched for the first time (cold start).
    handle_cold_start : process(clk_main_i)
@@ -847,6 +863,14 @@ begin
          cart_reset_o    <= reset_core_int_n when cart_reset_counter = 0 and cart_res_flckr_ign = 0 else '1';
          cart_reset_oe_o <= not cart_reset_o;
 
+         -- The KCS power cartridge does not correctly recognize when asserting the RESET pin on
+         -- the cartridge port. Therefore, a work-around has been implemented: When the
+         -- cartridge is resert, the cartridge power (5V) is removed as well. However, when
+         -- de-asserting reset and re-enabling cartridge power, the cartridge needs some time
+         -- before the power distribution is stable. Therefore, a pause is inserted where the
+         -- C64 core is held in reset for an additional short period (10 ms), see reset_core_delay.
+         cart_en_o       <= cart_reset_o;
+
          -- Connect physical output lines to the core's various output signals
          cart_roml_o     <= cart_roml_n;
          cart_romh_o     <= cart_romh_n;