Version 5.1 Release Candidate 3A (RC3A)

Implemented Antti Lukats' proposal to fix HyperRAM stability issue that manifest themselves on R6 boards.
MJoergen · Jun 21, 2024 · ce927cb · ce927cb
1 parent 7715d4d
commit ce927cb
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Showing 2 changed files with 22 additions and 7 deletions.
diff --git a/CORE/vhdl/config.vhd b/CORE/vhdl/config.vhd
@@ -77,7 +77,7 @@ type WHS_RECORD_ARRAY_TYPE is array (0 to WHS_RECORDS - 1) of WHS_RECORD_TYPE;
 
 constant SCR_WELCOME : string :=
 
-   "\n Commodore 64 for MEGA65 Version 5.1RC3\n\n" &
+   "\n Commodore 64 for MEGA65 Version 5.1RC3A\n\n" &
 
    " MiSTer port 2024 by MJoergen & sy2002\n" &
    " Powered by MiSTer2MEGA65\n\n\n" &
@@ -97,7 +97,7 @@ constant SCR_WELCOME : string :=
 
 constant HELP_1 : string :=
 
-   "\n Commodore 64 for MEGA65 Version 5.1RC3\n\n" &
+   "\n Commodore 64 for MEGA65 Version 5.1RC3A\n\n" &
 
    " MiSTer port 2024 by MJoergen & sy2002\n" &
    " Powered by MiSTer2MEGA65\n\n" &
@@ -128,7 +128,7 @@ constant HELP_1 : string :=
 
 constant HELP_2 : string :=
 
-   "\n Commodore 64 for MEGA65 Version 5.1RC3\n\n" &
+   "\n Commodore 64 for MEGA65 Version 5.1RC3A\n\n" &
 
    " When browsing the menu:\n\n" &
 
@@ -159,7 +159,7 @@ constant HELP_2 : string :=
 
 constant HELP_3 : string :=
 
-   "\n Commodore 64 for MEGA65 Version 5.1RC3\n\n" &
+   "\n Commodore 64 for MEGA65 Version 5.1RC3A\n\n" &
 
    " SID:\n\n" &
 
@@ -304,7 +304,7 @@ constant SEL_CORENAME      : std_logic_vector(15 downto 0) := x"0200";
 
 -- Currently this is only used in the debug console. Use the welcome screen and the
 -- help system to display the name and version of your core to the end user
-constant CORENAME          : string := "Commodore 64 for MEGA65 Version 5.1RC3";
+constant CORENAME          : string := "Commodore 64 for MEGA65 Version 5.1RC3A";
 
 --------------------------------------------------------------------------------------------------------------------
 -- "Help" menu / Options menu  (Selectors 0x0300 .. 0x0312): DO NOT TOUCH

diff --git a/M2M/vhdl/controllers/hyperram/hyperram_rx.vhd b/M2M/vhdl/controllers/hyperram/hyperram_rx.vhd
@@ -36,6 +36,7 @@ architecture synthesis of hyperram_rx is
 
    signal rwds_dq_in    : std_logic_vector(15 downto 0);
    signal rwds_in_delay : std_logic;
+   signal rwds_in_delay_idelay : std_logic;
 
    signal ctrl_dq_ie   : std_logic;
    signal ctrl_dq_ie_d : std_logic;
@@ -58,7 +59,7 @@ begin
       generic map (
          IDELAY_TYPE           => "FIXED",
          DELAY_SRC             => "IDATAIN",
-         IDELAY_VALUE          => 20,    -- Number of taps.
+         IDELAY_VALUE          => 12,    -- Number of taps: 6/21/24 sy2002 implemented Antti Lukats proposal
          HIGH_PERFORMANCE_MODE => "TRUE",
          SIGNAL_PATTERN        => "CLOCK",
          REFCLK_FREQUENCY      => 200.0, -- Each tap on average 5/32 ns.
@@ -76,9 +77,23 @@ begin
          idatain     => hr_rwds_in_i,
          datain      => '0',
          ldpipeen    => '0',
-         dataout     => rwds_in_delay,
+         dataout     => rwds_in_delay_idelay,
          cntvalueout => open
       ); -- delay_rwds_inst
+
+   -- 6/21/24 sy2002 implemented Antti Lukats proposal   
+   -- add local buffer, is faster than BUFG insertion!
+   BUFR_inst : BUFR
+   generic map (
+      BUFR_DIVIDE => "BYPASS",   -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
+      SIM_DEVICE => "7SERIES"    -- Must be set to "7SERIES"
+   )
+   port map (
+      O => rwds_in_delay,        -- 1-bit output: Clock output port
+      CE => '1',                 -- 1-bit input: Active high, clock enable (Divided modes only)
+      CLR => '0',                -- 1-bit input: Active high, asynchronous clear (Divided modes only)
+      I => rwds_in_delay_idelay  -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
+   );      
 
    -- Transfer the RWDS signal to the clk_i domain. This is used solely to determine the
    -- latency mode of the current transaction.