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XAPP495 proof concept TMDS in & out 1920 * 1080 * 60 Hz
Verilog VHDL
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DRAM16XN.v
README.md
chnlbond.v
clk.ucf
convert_30to15_fifo.v
decode.v
dvi_decoder.v
dvi_encoder.v
dvi_out.v
edid_rom.vhd
encode.v
hdmi_out.ucf
main.v
phsaligner.v
serdes_1_to_5_diff_data.v
serdes_n_to_1.v

README.md

XAPP495

Proof concept in, process, out signal by TMDS 1920 * 1080 * 60 Hz

UCF file for Digilent Atlys

NOTE: EDID file was replaced from AOT monitor for support 1920 * 1080 * 60

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