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Few improvements related to CPU cache line size and padding:
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Bug #79636: CACHE_LINE_SIZE should be 128 on AArch64
Bug #79637: Hard-coded cache line size
Bug #79638: Reconcile CACHE_LINE_SIZE with CPU_LEVEL1_DCACHE_LINESIZE
Bug #79652: Suspicious padding in srv_conc_t

- changed CPU_LEVEL1_DCACHE_LINESIZE to default to 128 bytes on POWER
  and AArch64 architectures in cases when no value could be detected
  by CMake using getconf

- changed CACHE_LINE_SIZE definition in ut0counter.h to be an alias of
  CPU_LEVEL1_DCACHE_LINESIZE

- changed a number of hard-coded 64-byte cache line size values in the
  InnoDB code

- fixed insufficient padding for srv_conc members in srv0conc.cc

Ported to Mariadb by Daniel Black <daniel.black@au.ibm.com>
Added s390 cache size of 256 at same time.
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akopytov authored and Sergey Vojtovich committed Jun 7, 2016
1 parent 935033a commit 49ad084
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Showing 12 changed files with 49 additions and 32 deletions.
4 changes: 0 additions & 4 deletions cmake/cpu_info.cmake
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,3 @@ IF(GETCONF)
OUTPUT_VARIABLE CPU_LEVEL1_DCACHE_LINESIZE
)
ENDIF()
IF(CPU_LEVEL1_DCACHE_LINESIZE AND CPU_LEVEL1_DCACHE_LINESIZE GREATER 0)
ELSE()
SET(CPU_LEVEL1_DCACHE_LINESIZE 64)
ENDIF()
18 changes: 18 additions & 0 deletions include/my_global.h
Original file line number Diff line number Diff line change
Expand Up @@ -1232,4 +1232,22 @@ static inline double rint(double x)
#undef __GNUG__
#endif

/*
Provide defaults for the CPU cache line size, if it has not been detected by
CMake using getconf
*/
#if !defined(CPU_LEVEL1_DCACHE_LINESIZE) || CPU_LEVEL1_DCACHE_LINESIZE == 0
#if CPU_LEVEL1_DCACHE_LINESIZE == 0
#undef CPU_LEVEL1_DCACHE_LINESIZE
#endif

#if defined(__s390__)
#define CPU_LEVEL1_DCACHE_LINESIZE 256
#elif defined(__powerpc__) || defined(__aarch64__)
#define CPU_LEVEL1_DCACHE_LINESIZE 128
#else
#define CPU_LEVEL1_DCACHE_LINESIZE 64
#endif
#endif

#endif /* my_global_h */
4 changes: 2 additions & 2 deletions storage/innobase/btr/btr0sea.cc
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ UNIV_INTERN ulint btr_search_this_is_zero = 0;
/** padding to prevent other memory update
hotspots from residing on the same memory
cache line as btr_search_latch */
UNIV_INTERN byte btr_sea_pad1[64];
UNIV_INTERN byte btr_sea_pad1[CACHE_LINE_SIZE];

/** The latch protecting the adaptive search system: this latch protects the
(1) positions of records on those pages where a hash index has been built.
Expand All @@ -67,7 +67,7 @@ UNIV_INTERN rw_lock_t* btr_search_latch_temp;

/** padding to prevent other memory update hotspots from residing on
the same memory cache line */
UNIV_INTERN byte btr_sea_pad2[64];
UNIV_INTERN byte btr_sea_pad2[CACHE_LINE_SIZE];

/** The adaptive hash index */
UNIV_INTERN btr_search_sys_t* btr_search_sys;
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2 changes: 1 addition & 1 deletion storage/innobase/include/log0log.h
Original file line number Diff line number Diff line change
Expand Up @@ -784,7 +784,7 @@ struct log_group_t{

/** Redo log buffer */
struct log_t{
byte pad[64]; /*!< padding to prevent other memory
byte pad[CACHE_LINE_SIZE]; /*!< padding to prevent other memory
update hotspots from residing on the
same memory cache line */
lsn_t lsn; /*!< log sequence number */
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12 changes: 8 additions & 4 deletions storage/innobase/include/ut0counter.h
Original file line number Diff line number Diff line change
Expand Up @@ -32,11 +32,15 @@ Created 2012/04/12 by Sunny Bains
#include "os0thread.h"

/** CPU cache line size */
#ifdef __powerpc__
#define CACHE_LINE_SIZE 128
#ifndef UNIV_HOTBACKUP
# ifdef CPU_LEVEL1_DCACHE_LINESIZE
# define CACHE_LINE_SIZE CPU_LEVEL1_DCACHE_LINESIZE
# else
# error CPU_LEVEL1_DCACHE_LINESIZE is undefined
# endif /* CPU_LEVEL1_DCACHE_LINESIZE */
#else
#define CACHE_LINE_SIZE 64
#endif
# define CACHE_LINE_SIZE 64
#endif /* UNIV_HOTBACKUP */

/** Default number of slots to use in ib_counter_t */
#define IB_N_SLOTS 64
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2 changes: 1 addition & 1 deletion storage/innobase/srv/srv0conc.cc
Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ UNIV_INTERN mysql_pfs_key_t srv_conc_mutex_key;

/** Variables tracking the active and waiting threads. */
struct srv_conc_t {
char pad[64 - (sizeof(ulint) + sizeof(lint))];
char pad[CACHE_LINE_SIZE - (sizeof(ulint) + sizeof(lint))];

/** Number of transactions that have declared_to_be_inside_innodb set.
It used to be a non-error for this value to drop below zero temporarily.
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4 changes: 2 additions & 2 deletions storage/xtradb/btr/btr0sea.cc
Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,7 @@ UNIV_INTERN ulint btr_search_this_is_zero = 0;
/** padding to prevent other memory update
hotspots from residing on the same memory
cache line as btr_search_latch */
UNIV_INTERN byte btr_sea_pad1[64];
UNIV_INTERN byte btr_sea_pad1[CACHE_LINE_SIZE];

/** Array of latches protecting individual AHI partitions. The latches
protect: (1) positions of records on those pages where a hash index from the
Expand All @@ -69,7 +69,7 @@ UNIV_INTERN prio_rw_lock_t* btr_search_latch_arr;

/** padding to prevent other memory update hotspots from residing on
the same memory cache line */
UNIV_INTERN byte btr_sea_pad2[64];
UNIV_INTERN byte btr_sea_pad2[CACHE_LINE_SIZE];

/** The adaptive hash index */
UNIV_INTERN btr_search_sys_t* btr_search_sys;
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2 changes: 1 addition & 1 deletion storage/xtradb/include/log0log.h
Original file line number Diff line number Diff line change
Expand Up @@ -857,7 +857,7 @@ struct log_group_t{

/** Redo log buffer */
struct log_t{
byte pad[64]; /*!< padding to prevent other memory
byte pad[CACHE_LINE_SIZE]; /*!< padding to prevent other memory
update hotspots from residing on the
same memory cache line */
lsn_t lsn; /*!< log sequence number */
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14 changes: 7 additions & 7 deletions storage/xtradb/include/trx0sys.h
Original file line number Diff line number Diff line change
Expand Up @@ -674,17 +674,17 @@ struct trx_sys_t{
trx_id_t max_trx_id; /*!< The smallest number not yet
assigned as a transaction id or
transaction number */
char pad1[64]; /*!< Ensure max_trx_id does not share
char pad1[CACHE_LINE_SIZE]; /*!< Ensure max_trx_id does not share

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@janlindstrom

janlindstrom Jun 7, 2016

Contributor

These padding's do not exist on storage/innobase/include/trx0sys.h, should we still add them ?

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@svoj

svoj Jun 7, 2016

Were they added by Percona? I don't have any data that would justify or discredit these paddings.

cache line with other fields. */
trx_id_t* descriptors; /*!< Array of trx descriptors */
ulint descr_n_max; /*!< The current size of the descriptors
array. */
char pad2[64]; /*!< Ensure static descriptor fields
char pad2[CACHE_LINE_SIZE]; /*!< Ensure static descriptor fields
do not share cache lines with
descr_n_used */
ulint descr_n_used; /*!< Number of used elements in the
descriptors array. */
char pad3[64]; /*!< Ensure descriptors do not share
char pad3[CACHE_LINE_SIZE]; /*!< Ensure descriptors do not share
cache line with other fields */
#ifdef UNIV_DEBUG
trx_id_t rw_max_trx_id; /*!< Max trx id of read-write transactions
Expand All @@ -694,7 +694,7 @@ struct trx_sys_t{
memory read-write transactions, sorted
on trx id, biggest first. Recovered
transactions are always on this list. */
char pad4[64]; /*!< Ensure list base nodes do not
char pad4[CACHE_LINE_SIZE]; /*!< Ensure list base nodes do not
share cache line with other fields */
trx_list_t ro_trx_list; /*!< List of active and committed in
memory read-only transactions, sorted
Expand All @@ -703,7 +703,7 @@ struct trx_sys_t{
is not necessary. We should exploit
this and increase concurrency during
add/remove. */
char pad5[64]; /*!< Ensure list base nodes do not
char pad5[CACHE_LINE_SIZE]; /*!< Ensure list base nodes do not
share cache line with other fields */
trx_list_t mysql_trx_list; /*!< List of transactions created
for MySQL. All transactions on
Expand All @@ -717,14 +717,14 @@ struct trx_sys_t{
mysql_trx_list may additionally contain
transactions that have not yet been
started in InnoDB. */
char pad6[64]; /*!< Ensure list base nodes do not
char pad6[CACHE_LINE_SIZE]; /*!< Ensure list base nodes do not
share cache line with other fields */
trx_list_t trx_serial_list;
/*!< trx->no ordered List of
transactions in either TRX_PREPARED or
TRX_ACTIVE which have already been
assigned a serialization number */
char pad7[64]; /*!< Ensure list base nodes do not
char pad7[CACHE_LINE_SIZE]; /*!< Ensure list base nodes do not
share cache line with other fields */
trx_rseg_t* const rseg_array[TRX_SYS_N_RSEGS];
/*!< Pointer array to rollback
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12 changes: 8 additions & 4 deletions storage/xtradb/include/ut0counter.h
Original file line number Diff line number Diff line change
Expand Up @@ -32,11 +32,15 @@ Created 2012/04/12 by Sunny Bains
#include "os0thread.h"

/** CPU cache line size */
#ifdef __powerpc__
#define CACHE_LINE_SIZE 128
#ifndef UNIV_HOTBACKUP
# ifdef CPU_LEVEL1_DCACHE_LINESIZE
# define CACHE_LINE_SIZE CPU_LEVEL1_DCACHE_LINESIZE
# else
# error CPU_LEVEL1_DCACHE_LINESIZE is undefined
# endif /* CPU_LEVEL1_DCACHE_LINESIZE */
#else
#define CACHE_LINE_SIZE 64
#endif
# define CACHE_LINE_SIZE 64
#endif /* UNIV_HOTBACKUP */

/** Default number of slots to use in ib_counter_t */
#define IB_N_SLOTS 64
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2 changes: 1 addition & 1 deletion storage/xtradb/srv/srv0conc.cc
Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,7 @@ UNIV_INTERN mysql_pfs_key_t srv_conc_mutex_key;

/** Variables tracking the active and waiting threads. */
struct srv_conc_t {
char pad[64 - (sizeof(ulint) + sizeof(lint))];
char pad[CACHE_LINE_SIZE - (sizeof(ulint) + sizeof(lint))];

/** Number of transactions that have declared_to_be_inside_innodb set.
It used to be a non-error for this value to drop below zero temporarily.
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5 changes: 0 additions & 5 deletions storage/xtradb/srv/srv0srv.cc
Original file line number Diff line number Diff line change
Expand Up @@ -580,11 +580,6 @@ UNIV_INTERN ib_uint64_t srv_index_page_decompressed = 0;

/* Ensure status variables are on separate cache lines */

#ifdef __powerpc__
#define CACHE_LINE_SIZE 128
#else
#define CACHE_LINE_SIZE 64
#endif
#define CACHE_ALIGNED __attribute__ ((aligned (CACHE_LINE_SIZE)))

UNIV_INTERN byte
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