In 2021 I started a repo to document my journey into HPC in road-to-plus-plus. This repo is focussed on FPGA and hardware design.
- Synthesis Experiment with synthesis with Yosys
- Fusesoc Experiments with fusesoc
- High Level Synthesis Experiments with High Level Synthesis
Open Source Verilog compiler https://github.com/steveicarus/iverilog
Tutorials:
- http://asic-world.com/verilog/veritut.html
- https://nandland.com/introduction-to-verilog-for-beginners-with-code-examples/
- https://www.fpga4fun.com/
- https://zipcpu.com/tutorial/
- https://www.fpga4fun.com/HDLtutorials.html
- https://verilogguide.readthedocs.io/en/latest/index.html
- Verilator https://www.veripool.org/verilator/#
- https://makerchip.com/
- https://github.com/os-fpga/GettingStartedWithFPGAs
- https://fpgatutorial.com/open-source-fpga-tools/
Tiny FPGA https://tinyfpga.com/
- https://opencores.org/
- https://alchitry.com/projects/gpu
- https://alchitry.com/memory-mapping-verilog
RISC V Rocketchip Bootcamp Available Node Types in rocketchip Diplomatic adder
- A Crash Course in the Diplomacy Framework
- Diplomacy and Tileset Reference
- Available Node Types in rocketchip
- Diplomatic adder
- LLVM Circt
- Sifive chisel to circt
- Adds a Chisel stage that generates LLVM circt
- Running Identical Threads in C-Slow Retiming based Designs for Functional Failure Detection
- Time and area efficient pattern matching on FPGAs
- A Configurable Hardware Fault Injection Framework for RISC-V Systems
- Vitis https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html
- Vivado https://www.xilinx.com/products/design-tools/vivado.html
- Digilent Adept https://digilent.com/shop/software/digilent-adept/
- This is available in Raspberry PI