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fixed problem where runMain gbvga.GbVgaDriver failed #1

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merged 1 commit into from Nov 3, 2020
Merged

fixed problem where runMain gbvga.GbVgaDriver failed #1

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4 changes: 2 additions & 2 deletions chisel/build.sbt
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Expand Up @@ -42,8 +42,8 @@ resolvers ++= Seq(

// Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
val defaultVersions = Map(
"chisel3" -> "3.4.0-RC1",
"chisel-iotesters" -> "1.5.0-RC1",
"chisel3" -> "3.4-SNAPSHOT",
"chisel-iotesters" -> "1.5-SNAPSHOT",
"chisel-formal" -> "0.1-SNAPSHOT",
)

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2 changes: 1 addition & 1 deletion chisel/src/main/scala/gbvga/gbinclude.scala
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Expand Up @@ -17,7 +17,7 @@ class Gb extends Bundle {
val data = UInt(2.W)
}

object GbConst {
trait GbConst { self: RawModule =>
val GBWIDTH = 160
val GBHEIGHT = 144

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2 changes: 0 additions & 2 deletions chisel/src/main/scala/gbvga/gbvga.scala
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Expand Up @@ -4,8 +4,6 @@ import chisel3._
import chisel3.util._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}

import GbConst._

class GbVga extends Module {
val io = IO(new Bundle {
/* Game boy input signals */
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4 changes: 1 addition & 3 deletions chisel/src/main/scala/gbvga/gbwrite.scala
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Expand Up @@ -5,11 +5,9 @@ import chisel3.util._
import chisel3.formal._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}

import GbConst._

class GbWrite (val datawidth: Int = 2,
val debug_simu: Boolean = true,
val aformal: Boolean = false) extends Module {//with Formal {
val aformal: Boolean = false) extends Module with GbConst {//with Formal {
val io = IO(new Bundle {
/* GameBoy input */
val gb = Input(new Gb())
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2 changes: 0 additions & 2 deletions chisel/src/main/scala/gbvga/hvsync.scala
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Expand Up @@ -11,8 +11,6 @@ import chisel3.util._
import chisel3.formal.Formal
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}

import GbConst._

class HVSync extends Module { // with Formal { scala version problem
val io = IO(new Bundle {
val hsync = Output(Bool())
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33 changes: 16 additions & 17 deletions chisel/src/main/scala/gbvga/memvga.scala
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Expand Up @@ -4,9 +4,8 @@ import chisel3._
import chisel3.util._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}

import GbConst._

class MemVga extends Module {
class MemVga extends Module with GbConst {
val io = IO(new Bundle {
/* memory read interface */
val mem_addr = Output(UInt((log2Ceil(GBWIDTH*GBHEIGHT)).W))
Expand Down Expand Up @@ -84,21 +83,21 @@ class MemVga extends Module {
/* Vga colors */
io.vga_color := VGA_BLACK
when(hvsync.io.display_on && (state===sPixInc)){
// io.vga_color := GbColors(io.mem_data)
switch(io.mem_data) {
is("b00".U) {
io.vga_color := GB_GREEN0
}
is("b01".U) {
io.vga_color := GB_GREEN1
}
is("b10".U) {
io.vga_color := GB_GREEN2
}
is("b11".U) {
io.vga_color := GB_GREEN3
}
}
io.vga_color := GbColors(io.mem_data)
// switch(io.mem_data) {
// is("b00".U) {
// io.vga_color := GB_GREEN0
// }
// is("b01".U) {
// io.vga_color := GB_GREEN1
// }
// is("b10".U) {
// io.vga_color := GB_GREEN2
// }
// is("b11".U) {
// io.vga_color := GB_GREEN3
// }
// }
}

/* Memory interface */
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4 changes: 1 addition & 3 deletions chisel/src/main/scala/gbvga/rawgbvga.scala
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Expand Up @@ -9,9 +9,7 @@ import chisel3.util._
import chisel3.formal.Formal
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}

import GbConst._

class RawGbVga extends RawModule {
class RawGbVga extends RawModule with GbConst {

/************/
/** outputs */
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2 changes: 0 additions & 2 deletions chisel/src/main/scala/gbvga/simplevga.scala
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Expand Up @@ -9,8 +9,6 @@ import chisel3.util._
import chisel3.formal.Formal
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}

import GbConst._

class SimpleVGA extends RawModule {
/************/
/** outputs */
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