Mi-V-Soft-RISC-V · seb-slowik · Aug 5, 2020 · Aug 5, 2020 · Nov 17, 2020 · Nov 17, 2020
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Avalanche_MIV_RV32_DGC2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Avalanche_MIV_RV32_DGC2_BaseDesign.job
diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md
@@ -1,6 +1,6 @@
 ## Future Avalanche Board FPGA Programming Files
 
-This folder contains FlashPro Express v2021.2 projects for the Future Avalanche Board Mi-V sample designs.
+This folder contains FlashPro Express v2021.3 projects for the Future Avalanche Board Mi-V sample designs.
 
 ## FlashPro Express
 The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.
@@ -20,6 +20,12 @@ The programming files contained under this folder were exported from the designs
     8. Once complete the status bar will display "1 PROGRAMMER(S) PASSED"
 
 ## Design Features
+
+> MI-V Extended Subsystem Design Guide Configurations:
+> * For **DGC2: I2C Write & Boot** design features, refer to [DGC2 README](import/components/IMC_DGC2/README.md)
+
+The following applies only to non MIV_ESS Design Guide: Design Guide Configurations (DGC2)
+
 The Libero designs include the following features:
 * A soft RISC-V processor.
 * A RISC-V debug block allowing on-target debug using SoftConsole

diff --git a/Libero_Projects/PF_Avalanche_ES_MIV_RV32IMAF_BaseDesign.tcl b/Libero_Projects/PF_Avalanche_ES_MIV_RV32IMAF_BaseDesign.tcl
@@ -70,7 +70,7 @@ proc  legacy_core_msg { }\
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 }
 
-proc download_cores_all_cfgs  { }\
+proc download_required_direct_cores  { }\
 {
 	download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
@@ -80,25 +80,22 @@ proc download_cores_all_cfgs  { }\
 	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
-	download_core -vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:1.2.108} -location {www.microchip-ip.com/repositories/SgCore} 
-	download_core -vlnv {Actel:SgCore:PF_OSC:1.0.102} -location {www.microchip-ip.com/repositories/SgCore}
-	download_core -vlnv {Actel:SgCore:PF_INIT_MONITOR:2.0.204} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} 
 	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
 	download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
-	download_core -vlnv {Actel:SgCore:PF_CCC:2.2.100} -location {www.microchip-ip.com/repositories/SgCore}
-	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
 }
 
 proc pre_configure_place_and_route { }\
 {
-	# Configuring Place_and_Route tool for a timing pass.
+	#Configuring Place_and_Route tool for a timing pass.
 	configure_tool -name {PLACEROUTE} -params {EFFORT_LEVEL:true} -params {REPAIR_MIN_DELAY:true} -params {TDPR:true} -params {IOREG_COMBINING:true}
 }
 
 proc run_verify_timing { }\
 {
+	#Runs Verify Timing tool
 	run_tool -name {VERIFYTIMING}	
 }
 
@@ -108,7 +105,7 @@ if {"$config" == "CFG1"} then {
 	} else {
 		create_new_project_label
 		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
-		download_cores_all_cfgs
+		download_required_direct_cores
 		source ./import/components/IMAF_CFG1/import_component_and_constraints_pf_avalanche_rv32imaf_cfg1.tcl
 		save_project
         base_design_built
@@ -122,7 +119,7 @@ if {"$config" == "CFG1"} then {
 		no_first_argument_entered
 		create_new_project_label
 		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
-		download_cores_all_cfgs
+		download_required_direct_cores
 		source ./import/components/IMAF_CFG1/import_component_and_constraints_pf_avalanche_rv32imaf_cfg1.tcl
 		save_project
         base_design_built

diff --git a/Libero_Projects/PF_Avalanche_ES_MIV_RV32IMA_BaseDesign.tcl b/Libero_Projects/PF_Avalanche_ES_MIV_RV32IMA_BaseDesign.tcl
@@ -74,7 +74,7 @@ proc  legacy_core_msg { }\
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 }
 
-proc download_cores_all_cfgs  { }\
+proc download_required_direct_cores  { }\
 {
 	download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
@@ -84,35 +84,38 @@ proc download_cores_all_cfgs  { }\
 	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
-	download_core -vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:1.2.108} -location {www.microchip-ip.com/repositories/SgCore} 
-	download_core -vlnv {Actel:SgCore:PF_OSC:1.0.102} -location {www.microchip-ip.com/repositories/SgCore}
-	download_core -vlnv {Actel:SgCore:PF_INIT_MONITOR:2.0.204} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} 
 	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
 	download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
-	download_core -vlnv {Actel:SgCore:PF_CCC:2.2.100} -location {www.microchip-ip.com/repositories/SgCore}
-	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
 }
 
 proc pre_configure_place_and_route { }\
 {
-	# Configuring Place_and_Route tool for a timing pass.
+	#Configuring Place_and_Route tool for a timing pass.
 	configure_tool -name {PLACEROUTE} -params {EFFORT_LEVEL:true} -params {REPAIR_MIN_DELAY:true} -params {TDPR:true} -params {IOREG_COMBINING:true}
 }
 
 proc run_verify_timing { }\
 {
+	#Runs Verify Timing tool
 	run_tool -name {VERIFYTIMING}	
 }
 
+proc increase_loop_limit { }\
+{
+	#Increase the loop limit in Synplify
+	configure_tool -name {SYNTHESIZE} -params {SYNPLIFY_OPTIONS:set_option -looplimit 4000} 
+}
+
 if {"$config" == "CFG1"} then {
 	if {[file exists $project_dir_CFG1] == 1} then {
 		project_exists
 	} else {
 		create_new_project_label
 		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
-		download_cores_all_cfgs
+		download_required_direct_cores
 		source ./import/components/IMA_CFG1/import_component_and_constraints_pf_avalanche_rv32ima_cfg1.tcl
 		save_project
         base_design_built
@@ -123,7 +126,7 @@ if {"$config" == "CFG1"} then {
 	} else {
 		create_new_project_label
 		new_project -location $project_dir_CFG2 -name $Libero_project_name_CFG2 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
-		download_cores_all_cfgs
+		download_required_direct_cores
 		source ./import/components/IMA_CFG2/import_component_and_constraints_pf_avalanche_rv32ima_cfg2.tcl
 		save_project
         base_design_built
@@ -137,7 +140,7 @@ if {"$config" == "CFG1"} then {
 		no_first_argument_entered
 		create_new_project_label
 		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
-		download_cores_all_cfgs
+		download_required_direct_cores
 		source ./import/components/IMA_CFG1/import_component_and_constraints_pf_avalanche_rv32ima_cfg1.tcl
 		save_project
         base_design_built
@@ -147,7 +150,7 @@ if {"$config" == "CFG1"} then {
 pre_configure_place_and_route
 
 if {"$config" == "CFG2"} then {
-	configure_tool -name {SYNTHESIZE} -params {SYNPLIFY_OPTIONS:set_option -looplimit 4000} 
+	increase_loop_limit
 }
 
 if {"$design_flow_stage" == "SYNTHESIZE"} then {

diff --git a/Libero_Projects/PF_Avalanche_ES_MIV_RV32_BaseDesign.tcl b/Libero_Projects/PF_Avalanche_ES_MIV_RV32_BaseDesign.tcl
@@ -68,7 +68,7 @@ proc  base_design_built { }\
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 }
 
-proc download_cores_all_cfgs  { }\
+proc download_required_direct_cores  { }\
 {
 	download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
@@ -78,25 +78,22 @@ proc download_cores_all_cfgs  { }\
 	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
-	download_core -vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:1.2.108} -location {www.microchip-ip.com/repositories/SgCore} 
-	download_core -vlnv {Actel:SgCore:PF_OSC:1.0.102} -location {www.microchip-ip.com/repositories/SgCore}
-	download_core -vlnv {Actel:SgCore:PF_INIT_MONITOR:2.0.204} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} 
 	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
 	download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
-	download_core -vlnv {Actel:SgCore:PF_CCC:2.2.100} -location {www.microchip-ip.com/repositories/SgCore}
-	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
 }
 
 proc pre_configure_place_and_route { }\
 {
-	# Configuring Place_and_Route tool for a timing pass.
+	#Configuring Place_and_Route tool for a timing pass.
 	configure_tool -name {PLACEROUTE} -params {EFFORT_LEVEL:true} -params {REPAIR_MIN_DELAY:true} -params {TDPR:true} -params {IOREG_COMBINING:true}
 }
 
 proc run_verify_timing { }\
 {
+	#Runs Verify Timing tool
 	run_tool -name {VERIFYTIMING}	
 }
 
@@ -106,7 +103,7 @@ if {"$config" == "CFG1"} then {
 	} else {
 		create_new_project_label
 		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
-		download_cores_all_cfgs
+		download_required_direct_cores
 		source ./import/components/IMC_CFG1/import_component_and_constraints_pf_avalanche_rv32imc_cfg1.tcl
 		save_project
         base_design_built
@@ -117,7 +114,7 @@ if {"$config" == "CFG1"} then {
 	} else {
 		create_new_project_label
 		new_project -location $project_dir_CFG2 -name $Libero_project_name_CFG2 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
-		download_cores_all_cfgs
+		download_required_direct_cores
 		source ./import/components/IMC_CFG2/import_component_and_constraints_pf_avalanche_rv32imc_cfg2.tcl
 		save_project
         base_design_built
@@ -128,7 +125,7 @@ if {"$config" == "CFG1"} then {
 	} else {
 		create_new_project_label
 		new_project -location $project_dir_CFG3 -name $Libero_project_name_CFG3 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
-		download_cores_all_cfgs
+		download_required_direct_cores
 		source ./import/components/IMC_CFG3/import_component_and_constraints_pf_avalanche_rv32imc_cfg3.tcl
 		save_project
         base_design_built
@@ -142,7 +139,7 @@ if {"$config" == "CFG1"} then {
 		no_first_argument_entered
 		create_new_project_label
 		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG484} -speed {STD} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
-		download_cores_all_cfgs
+		download_required_direct_cores
 		source ./import/components/IMC_CFG1/import_component_and_constraints_pf_avalanche_rv32imc_cfg1.tcl
 		save_project
         base_design_built