Lib. v2021.3 Update - DGC Readmes review PR #7
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All of the SgCore components used are now downloaded using the TCL wildcards for version numbers. This should allow for easier updating procedures of the Libero Scripted Designs in the future where files would not need to be edited manually to modify component's version numbers. This technique would only work if the component's ports have not changed. PF_INIT_MONITOR has been updated to v2.0.205 from v2.0.204 A function has been added to auto-arrange the SmartDesign layout after building. Signed-off by: Sebastian Slowikowski <seb.slowikowski@microchip.com>
Design Guide Configurations (DGC) using Mi-V Extended Subsystem (MIV_ESS) have been added to the top level MIV_RV32 TCL file for production silicon devices. MIV_ESS component replaces previously isolated peripheral components like CoreGPIOs and CoreUARTapb, it also provides additional peripherals. Refer the the READMEs for list of features. The function to download all latest cores has been modified to only download the required DirectCores for all of the supported configurations. Additional comments have been added and general formatting improved in all of the top lvl TCL files Signed-off by: Sebastian Slowikowski <seb.slowikowski@microchip.com>
GitHub readmes have been updated to reflect the new version of Libero SoC v2021.3 the scripts are compatible with. Readmes still require and update to reflect information on Design Guide Configurations. Signed-off by: Sebastian Slowikowski <seb.slowikowski@microchip.com>
DGC2 bitsteram has been added to FlashPro Express projects folder. An updated version of software project 'miv-rv32i-systick-blinky' was made available. The project is catered specifically for a MIV_ESS design setup. The blinky program is initially stored in the LSRAM in DGC Libero designs, before Bootstrap module performs its copying operations. The software configuration 'mivrv32i-Release' was used to generate the .hex program. TCL files have been updated to use the latest .hex. Author: Merijn van de Water <merijn.vandewater@microchip.com> Signed-off: Sebastian Slowikowski <seb.slowikowski@microchip.com>
An .elf file of a Bootloader software program for DGC2 has been added. A readme update is to follow with instructions on how to use the .elf program for copying data to external memories like SPI/I2C/uPROM and then to TCM via the TAS APB I/F on MIV_RV32. For this configuration the Bootstrap module copies data from LSRAM at 0x8000_0000 to I2C EEPROM found outside the fabric. The Bootstrap copies data from external I2C EEPROM to TCM and MIV_RV32 is allowed to boot from TCM. Author: Merijn van de Water <merijn.vandewater@microchip.com> Signed-off: Sebastian Slowikowski <seb.slowikowski@microchip.com>
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Libero Scripted Designs Update towards Libero SoC v2023.1 * MIV_RV32 in the designs has been updated from: v3.0.100 to v3.1.100. Some of the new features include: RISC-V F Extension and I-Cache. * Refactored TCL script library, updated for modularity, parameterization and input handling * New dynamic paths added, should allow for better performance on non-Windows based OS systems. * Design components are now downloaded dynamically for each design configuration * Removed glitches which may have been seen when adapting the designs for VHDL * Project folders for ES designs have been uniquified for traceability * Project folders for MIV_RV32, MIV_RV32IMAF and MIV_RV32IMA have been uniquified for clarity and traceability * Improved TCL output messaging with regards to the design building and design flow progression * An example software program has been added to LSRAM-based configurations. After programming the bitstream, software boots out of the box from the LSRAM. * The clocking circuitry in all of the designs has been improved. A new 50MHz clock reference for the CCC has been added by replacing the RC Oscillator. Timing has been improved across the designs. * FlashPro_Express_Projects have been updated to reflect the latest design changes Signed-off by: <seb.slowikowski@microchip.com> --------- Co-authored-by: CLappin <ciaran.lappin@microsemi.com>
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* LibSD Update for v2023.1 (#7) * Notice added to Libero_Project and FlashPro_Express_Projects regarding the work around for the MTVEC issue for FreeRTOS and the Fast Interrupt issue in the latest release of the MIV_RV32. Please read the readme files in each of those folders to see if you are effected. Libero Scripted Designs Update towards Libero SoC v2023.1 * MIV_RV32 in the designs has been updated from: v3.0.100 to v3.1.100. Some of the new features include: RISC-V F Extension and I-Cache. * Refactored TCL script library, updated for modularity, parameterization and input handling * New dynamic paths added, should allow for better performance on non-Windows based OS systems. * Design components are now downloaded dynamically for each design configuration * Removed glitches which may have been seen when adapting the designs for VHDL * Project folders for ES designs have been uniquified for traceability * Project folders for MIV_RV32, MIV_RV32IMAF and MIV_RV32IMA have been uniquified for clarity and traceability * Improved TCL output messaging with regards to the design building and design flow progression * An example software program has been added to LSRAM-based configurations. After programming the bitstream, software boots out of the box from the LSRAM. * The clocking circuitry in all of the designs has been improved. A new 50MHz clock reference for the CCC has been added by replacing the RC Oscillator. Timing has been improved across the designs. * FlashPro_Express_Projects have been updated to reflect the latest design changes Co-authored-by: Sebastian Slowikowski <55508128+seb-slowiko@users.noreply.github.com>
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