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Cleanup of overloaded tlm_gp
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@eyck
eyck committed Oct 18, 2017
1 parent db46dcd commit 1f2e587
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Showing 4 changed files with 87 additions and 387 deletions.
7 changes: 4 additions & 3 deletions incl/scc/tlm_target.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,11 +23,12 @@
#ifndef _SYSC_TLM_TARGET_H_
#define _SYSC_TLM_TARGET_H_

#include <array>
#include <scv4tlm/tlm_rec_target_socket.h>
#include <util/range_lut.h>
#include "scc/utilities.h"
#include "scv4tlm/tlm_rec_target_socket.h"
#include "util/range_lut.h"
#include "scc/resource_access_if.h"
#include "scc/target_mixin.h"
#include <array>

namespace scc {
/**
Expand Down
80 changes: 44 additions & 36 deletions incl/scv4tlm/tlm2_recorder.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,7 @@ template <typename TYPES = tlm::tlm_base_protocol_types>
class tlm2_recorder : public virtual tlm::tlm_fw_transport_if<TYPES>,
public virtual tlm::tlm_bw_transport_if<TYPES>,
public sc_core::sc_object {
const std::regex pat{"_rec$"};
public:
SC_HAS_PROCESS(tlm2_recorder<TYPES>);

Expand Down Expand Up @@ -119,7 +120,8 @@ class tlm2_recorder : public virtual tlm::tlm_fw_transport_if<TYPES>,
, dmi_streamHandle(NULL)
, dmi_trGetHandle(NULL)
, dmi_trInvalidateHandle(NULL)
, extensionRecording(NULL) {}
, extensionRecording(NULL)
, fixed_basename(regex_replace(sc_core::sc_object::name(), pat, "")){}

virtual ~tlm2_recorder() override {
delete b_streamHandle;
Expand Down Expand Up @@ -327,10 +329,7 @@ class tlm2_recorder : public virtual tlm::tlm_fw_transport_if<TYPES>,

tlm2_extensions_recording_if<TYPES> *extensionRecording;

std::string get_fixed_basename() {
static const std::regex pat("_rec$");
return regex_replace(std::string(this->name()), pat, "");
}
const std::string fixed_basename;
};

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
Expand All @@ -345,8 +344,7 @@ void tlm2_recorder<TYPES>::b_transport(typename TYPES::tlm_payload_type &trans,
return;
}
if (b_streamHandle == NULL) {
string basename(get_fixed_basename());
b_streamHandle = new scv_tr_stream((basename + ".blocking").c_str(), "TRANSACTOR", m_db);
b_streamHandle = new scv_tr_stream((fixed_basename + "_bl").c_str(), "TRANSACTOR", m_db);
b_trHandle[tlm::TLM_READ_COMMAND] =
new scv_tr_generator<sc_dt::uint64, sc_dt::uint64>("read", *b_streamHandle, "start_delay", "end_delay");
b_trHandle[tlm::TLM_WRITE_COMMAND] =
Expand Down Expand Up @@ -384,7 +382,7 @@ void tlm2_recorder<TYPES>::b_transport(typename TYPES::tlm_payload_type &trans,
} else {
h.add_relation(rel_str(PREDECESSOR_SUCCESSOR), preExt->txHandle);
}
scv_tr_handle preTx(preExt->txHandle);
scv_tr_handle preTx{preExt->txHandle};
preExt->txHandle = h;
fw_port->b_transport(trans, delay);
trans.get_extension(preExt);
Expand All @@ -396,9 +394,17 @@ void tlm2_recorder<TYPES>::b_transport(typename TYPES::tlm_payload_type &trans,
preExt->txHandle = preTx;
}

tgd.set_response_status(trans.get_response_status());
tgd.response_status=trans.get_response_status();
if(trans.get_command()==tlm::TLM_READ_COMMAND)

h.record_attribute("trans", tgd);
h.record_attribute("trans.data_value", *(uint64_t *)trans.get_data_ptr());
if(tgd.data_length<8){
uint64_t buf=0;
//FIXME: this is endianess dependent
for(size_t i = 0; i<tgd.data_length; i++)
buf+=(*tgd.data)<<i*8;
h.record_attribute("trans.data_value", buf);
}
if (extensionRecording) extensionRecording->recordEndTx(h, trans);
// End the transaction
b_trHandle[trans.get_command()]->end_transaction(h, delay.value(), sc_time_stamp());
Expand All @@ -416,8 +422,7 @@ template <typename TYPES>
void tlm2_recorder<TYPES>::btx_cb(tlm_recording_payload &rec_parts, const typename TYPES::tlm_phase_type &phase) {
scv_tr_handle h;
if (b_trTimedHandle[0] == NULL) {
std::string basename(get_fixed_basename());
b_streamHandleTimed = new scv_tr_stream((basename + ".bl_t_ann").c_str(), "TRANSACTOR", m_db);
b_streamHandleTimed = new scv_tr_stream((fixed_basename + "_bl_timed").c_str(), "TRANSACTOR", m_db);
b_trTimedHandle[0] =
new scv_tr_generator<tlm::tlm_command, tlm::tlm_response_status>("read", *b_streamHandleTimed);
b_trTimedHandle[1] =
Expand Down Expand Up @@ -461,8 +466,7 @@ tlm::tlm_sync_enum tlm2_recorder<TYPES>::nb_transport_fw(typename TYPES::tlm_pay
if (!isRecordingEnabled()) return fw_port->nb_transport_fw(trans, phase, delay);
// initialize stream and generator if not yet done
if (nb_streamHandle[FW] == NULL) {
string basename(get_fixed_basename());
nb_streamHandle[FW] = new scv_tr_stream((basename + ".nb_forward").c_str(), "TRANSACTOR", m_db);
nb_streamHandle[FW] = new scv_tr_stream((fixed_basename + "_nb_fw").c_str(), "TRANSACTOR", m_db);
nb_fw_trHandle[tlm::TLM_READ_COMMAND] = new scv_tr_generator<tlm::tlm_phase_enum, tlm::tlm_sync_enum>(
"read", *nb_streamHandle[FW], "tlm_phase", "tlm_sync");
nb_fw_trHandle[tlm::TLM_WRITE_COMMAND] = new scv_tr_generator<tlm::tlm_phase_enum, tlm::tlm_sync_enum>(
Expand Down Expand Up @@ -508,8 +512,14 @@ tlm::tlm_sync_enum tlm2_recorder<TYPES>::nb_transport_fw(typename TYPES::tlm_pay
/*************************************************************************
* handle recording
*************************************************************************/
tgd.set_response_status(trans.get_response_status());
tgd.response_status=trans.get_response_status();
h.record_attribute("trans", tgd);
if(tgd.data_length<8){
uint64_t buf=0;
//FIXME: this is endianess dependent
for(size_t i = 0; i<tgd.data_length; i++) buf+=(*tgd.data)<<i*8;
h.record_attribute("trans.data_value", buf);
}
if (extensionRecording) extensionRecording->recordEndTx(h, trans);
h.record_attribute("tlm_phase[return_path]", (tlm::tlm_phase_enum)(unsigned)phase);
h.record_attribute("delay[return_path]", delay.to_string());
Expand Down Expand Up @@ -547,8 +557,7 @@ tlm::tlm_sync_enum tlm2_recorder<TYPES>::nb_transport_bw(typename TYPES::tlm_pay
sc_core::sc_time &delay) {
if (!isRecordingEnabled()) return bw_port->nb_transport_bw(trans, phase, delay);
if (nb_streamHandle[BW] == NULL) {
string basename(get_fixed_basename());
nb_streamHandle[BW] = new scv_tr_stream((basename + ".nb_backward").c_str(), "TRANSACTOR", m_db);
nb_streamHandle[BW] = new scv_tr_stream((fixed_basename + "_nb_bw").c_str(), "TRANSACTOR", m_db);
nb_bw_trHandle[0] = new scv_tr_generator<tlm::tlm_phase_enum, tlm::tlm_sync_enum>("read", *nb_streamHandle[BW],
"tlm_phase", "tlm_sync");
nb_bw_trHandle[1] = new scv_tr_generator<tlm::tlm_phase_enum, tlm::tlm_sync_enum>("write", *nb_streamHandle[BW],
Expand Down Expand Up @@ -588,8 +597,14 @@ tlm::tlm_sync_enum tlm2_recorder<TYPES>::nb_transport_bw(typename TYPES::tlm_pay
/*************************************************************************
* handle recording
*************************************************************************/
tgd.set_response_status(trans.get_response_status());
tgd.response_status=trans.get_response_status();
h.record_attribute("trans", tgd);
if(tgd.data_length<8){
uint64_t buf=0;
//FIXME: this is endianess dependent
for(size_t i = 0; i<tgd.data_length; i++) buf+=(*tgd.data)<<i*8;
h.record_attribute("trans.data_value", buf);
}
if (extensionRecording) extensionRecording->recordEndTx(h, trans);
// phase and delay are already recorded
h.record_attribute("phase_upd", (tlm::tlm_phase_enum)(unsigned)phase);
Expand Down Expand Up @@ -621,15 +636,13 @@ void tlm2_recorder<TYPES>::nbtx_cb(tlm_recording_payload &rec_parts, const typen
scv_tr_handle h;
std::map<uint64, scv_tr_handle>::iterator it;
if (nb_streamHandleTimed[FW] == NULL) {
std::string basename(get_fixed_basename());
nb_streamHandleTimed[FW] = new scv_tr_stream((basename + ".nb_req_t_ann").c_str(), "TRANSACTOR", m_db);
nb_streamHandleTimed[FW] = new scv_tr_stream((fixed_basename + "_nb_req_timed").c_str(), "TRANSACTOR", m_db);
nb_txReqHandle[0] = new scv_tr_generator<>("read", *nb_streamHandleTimed[FW]);
nb_txReqHandle[1] = new scv_tr_generator<>("write", *nb_streamHandleTimed[FW]);
nb_txReqHandle[2] = new scv_tr_generator<>("ignore", *nb_streamHandleTimed[FW]);
}
if (nb_streamHandleTimed[BW] == NULL) {
std::string basename(get_fixed_basename());
nb_streamHandleTimed[BW] = new scv_tr_stream((basename + ".nb_resp_t_ann").c_str(), "TRANSACTOR", m_db);
nb_streamHandleTimed[BW] = new scv_tr_stream((fixed_basename + "_nb_resp_timed").c_str(), "TRANSACTOR", m_db);
nb_txRespHandle[0] = new scv_tr_generator<>("read", *nb_streamHandleTimed[BW]);
nb_txRespHandle[1] = new scv_tr_generator<>("write", *nb_streamHandleTimed[BW]);
nb_txRespHandle[2] = new scv_tr_generator<>("ignore", *nb_streamHandleTimed[BW]);
Expand Down Expand Up @@ -701,14 +714,11 @@ bool tlm2_recorder<TYPES>::get_direct_mem_ptr(typename TYPES::tlm_payload_type &
if (!isRecordingEnabled()) {
return fw_port->get_direct_mem_ptr(trans, dmi_data);
}
if (dmi_streamHandle == NULL) {
string basename(get_fixed_basename());
dmi_streamHandle = new scv_tr_stream((basename + ".dmi").c_str(), "TRANSACTOR", m_db);
if (!dmi_streamHandle)
dmi_streamHandle = new scv_tr_stream((fixed_basename + "_dmi").c_str(), "TRANSACTOR", m_db);
if(!dmi_trGetHandle)
dmi_trGetHandle =
new scv_tr_generator<tlm_gp_data, tlm_dmi_data>("get_dmi_ptr", *b_streamHandle, "trans", "dmi_data");
dmi_trInvalidateHandle = new scv_tr_generator<sc_dt::uint64, sc_dt::uint64>("invalidate", *b_streamHandle,
"start_delay", "end_delay");
}
new scv_tr_generator<tlm_gp_data, tlm_dmi_data>("get_dmi_ptr", *dmi_streamHandle, "trans", "dmi_data");
scv_tr_handle h = dmi_trGetHandle->begin_transaction(tlm_gp_data(trans));
bool status = fw_port->get_direct_mem_ptr(trans, dmi_data);
dmi_trGetHandle->end_transaction(h, tlm_dmi_data(dmi_data));
Expand All @@ -726,14 +736,12 @@ void tlm2_recorder<TYPES>::invalidate_direct_mem_ptr(sc_dt::uint64 start_addr, s
bw_port->invalidate_direct_mem_ptr(start_addr, end_addr);
return;
}
if (dmi_streamHandle == NULL) {
string basename(get_fixed_basename());
dmi_streamHandle = new scv_tr_stream((basename + ".dmi").c_str(), "TRANSACTOR", m_db);
dmi_trGetHandle =
new scv_tr_generator<tlm_gp_data, tlm_dmi_data>("get_dmi_ptr", *b_streamHandle, "trans", "dmi_data");
dmi_trInvalidateHandle = new scv_tr_generator<sc_dt::uint64, sc_dt::uint64>("invalidate", *b_streamHandle,
if (!dmi_streamHandle)
dmi_streamHandle = new scv_tr_stream((fixed_basename + "_dmi").c_str(), "TRANSACTOR", m_db);
if(!dmi_trInvalidateHandle)
dmi_trInvalidateHandle = new scv_tr_generator<sc_dt::uint64, sc_dt::uint64>("invalidate_dmi_ptr", *dmi_streamHandle,
"start_delay", "end_delay");
}

scv_tr_handle h = dmi_trInvalidateHandle->begin_transaction(start_addr);
bw_port->invalidate_direct_mem_ptr(start_addr, end_addr);
dmi_trInvalidateHandle->end_transaction(h, end_addr);
Expand Down

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