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@Minres

MINRES Technologies GmbH

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  1. SystemC-Quickstart SystemC-Quickstart Public

    A simple C++ CMake project to jump-start development of SystemC models and systems

    C++ 21 3

  2. SystemC-Components SystemC-Components Public

    A SystemC productivity library: https://minres.github.io/SystemC-Components/

    JavaScript 94 25

  3. TGC-VP TGC-VP Public

    The Scale4Edge ecosystem VP

    C 8 4

  4. CoreDSL CoreDSL Public

    Xtext project to parse CoreDSL files

    Xtend 16 3

  5. PySysC PySysC Public

    Forked from accellera-official/PySysC

    Public repository for the SC Common Practices Subgroup

    Python 8 1

  6. SCViewer SCViewer Public

    Online documentation can be found at https://minres.github.io/SCViewer/

    Java 14 1

Repositories

Showing 10 of 44 repositories
  • TGC-ISS Public

    This is a mirror of the TGC-ISS

    Minres/TGC-ISS’s past year of commit activity
    CMake 0 BSD-3-Clause 0 0 0 Updated Nov 16, 2024
  • TGC-VP Public

    The Scale4Edge ecosystem VP

    Minres/TGC-VP’s past year of commit activity
    C 8 Apache-2.0 4 0 0 Updated Nov 16, 2024
  • SystemC-Quickstart Public

    A simple C++ CMake project to jump-start development of SystemC models and systems

    Minres/SystemC-Quickstart’s past year of commit activity
    C++ 21 Apache-2.0 3 0 0 Updated Nov 11, 2024
  • SystemC-Components Public

    A SystemC productivity library: https://minres.github.io/SystemC-Components/

    Minres/SystemC-Components’s past year of commit activity
    JavaScript 94 Apache-2.0 25 7 1 Updated Oct 10, 2024
  • DBT-RISE-RISCV Public

    An instruction set simulator based on DBT-RISE implementing the RISC-V ISA

    Minres/DBT-RISE-RISCV’s past year of commit activity
    C++ 34 BSD-3-Clause 15 1 0 Updated Oct 4, 2024
  • RISCV_ISA_CoreDSL Public

    CoreDSL descriptions of the RISC-V ISA

    Minres/RISCV_ISA_CoreDSL’s past year of commit activity
    4 Apache-2.0 11 3 0 Updated Oct 4, 2024
  • DBT-RISE-Core Public

    DBT-RISE - A versatile Dynamic Binary Translation (DBT) based environment to implement instruction set simulator (ISS)

    Minres/DBT-RISE-Core’s past year of commit activity
    C++ 9 BSD-3-Clause 3 1 0 Updated Sep 30, 2024
  • NaxRiscv Public Forked from SpinalHDL/NaxRiscv
    Minres/NaxRiscv’s past year of commit activity
    Scala 0 MIT 40 0 0 Updated Sep 25, 2024
  • RISCV-VP Public
    Minres/RISCV-VP’s past year of commit activity
    C++ 0 Apache-2.0 0 0 0 Updated Sep 25, 2024
  • tracy Public Forked from wolfpld/tracy

    Frame profiler

    Minres/tracy’s past year of commit activity
    C++ 0 695 0 0 Updated Aug 22, 2024
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