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fix: bus converter off by 1 when reading redwires
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MrTJP committed May 15, 2022
1 parent 4bdfe55 commit fb0ea91
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Showing 4 changed files with 7 additions and 5 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -380,7 +380,7 @@ class BusConverter extends BundledGatePart(GateType.BUS_CONVERTER)
var changed = false

val oldRSIn = rsIn
rsIn = if (shape == 0) getRedstoneInput(2)/17 else 0
rsIn = if (shape == 0) getAnalogRedstoneInput(2) else 0
if (oldRSIn != rsIn) changed = true

val oldBIn = bIn
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Original file line number Diff line number Diff line change
Expand Up @@ -119,6 +119,10 @@ abstract class RedstoneGatePart(gateType:GateType) extends GatePart(gateType) wi
else calcMaxSignal(ar, true, false)
}

def getAnalogRedstoneInput(r:Int):Int = {
(getRedstoneInput(r) + 16) / 17
}

override def resolveSignal(part:Any, r:Int) = part match
{
case re:IRedwireEmitter => re.getRedwireSignal(r)
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Original file line number Diff line number Diff line change
Expand Up @@ -696,8 +696,6 @@ class Comparator extends RedstoneGatePart(GateType.COMPARATOR) with INeighborTil
if (r == 0) state2&0xF
else 0

def getAnalogInput(r:Int):Int = (getRedstoneInput(r)+16)/17

def calcInputA:Int = {
//TODO comparator calculations may not be accurate anymore

Expand All @@ -708,7 +706,7 @@ class Comparator extends RedstoneGatePart(GateType.COMPARATOR) with INeighborTil
if (state.hasAnalogOutputSignal)
return state.getAnalogOutputSignal(world, pos)

var i = getAnalogInput(2)
var i = getAnalogRedstoneInput(2)

if (i < 15 && state.isRedstoneConductor(world, pos)) {
pos = pos.relative(absDir)
Expand Down Expand Up @@ -736,7 +734,7 @@ class Comparator extends RedstoneGatePart(GateType.COMPARATOR) with INeighborTil
if (list.size == 1) list.get(0) else null
}

def calcInput:Int = getAnalogInput(1)<<4|calcInputA<<8|getAnalogInput(3)<<12
def calcInput:Int = getAnalogRedstoneInput(1)<<4|calcInputA<<8|getAnalogRedstoneInput(3)<<12

def digitize(analog:Int):Int = {
var digital = 0
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