Pinned

1. aes_comb_sv aes_comb_sv Public

   Clock-less implementation of Advanced Encryption Standard (AES) using SystemVerilog

   SystemVerilog

2. AKVP_x09 AKVP_x09 Public

   My take on HCMUT's Department of Electronics' 9-bit processor.

   VHDL 5

3. Async_FIFO Async_FIFO Public

   My design of a hardware asynchronous FIFO.

   Verilog 1

4. Huge_Matrix_Multiplier Huge_Matrix_Multiplier Public

   My attempt to design a hardware matrix multiplier (using SystemVerilog) that multiplies very large matrices together, with as low clock cycles and as high clock speed as possible.

   Verilog

5. pipeline pipeline Public

   An upgrade from my previous single cycle RV32I design into a 5-stage pipeline.

   Verilog 1

6. SHAKE256_sv SHAKE256_sv Public

   Hardware (SystemVerilog) implementation of the SHAKE256, published in FIPS 202 by NIST.

   SystemVerilog 1