SystemVerilog Tester

The purpose of this project is to find all the supported and missing SystemVerilog features in various Verilog tools.

The report generated from the last passing master build can be viewed here.

Running

Initialize the submodules:

$ git submodule update --init --recursive

Build tools (optional, tools from PATH can be used):

make runners

And then just run:

$ make generate-tests -j$(nproc)
$ make -j$(nproc)

This should generate many log files for all the tools/tests combinations and an out/report.html file with a summary of the tested features and tools.

If you don't want to generate the report file, but are interested in just running all the tests, you can run:

make tests

Supported tools

• Yosys
• Odin II
• Verilator
• Icarus
• slang
• sv2v(zachjs)
• tree-sitter-verilog
• sv-parser
• hdlConvertor