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PhD student at MIET; RISC-V, Posit enthusiast;
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PhD student at MIET; RISC-V, Posit enthusiast;
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  1. risc-v_awesome_list risc-v_awesome_list Public

    45

  2. SimpleCacheController SimpleCacheController Public

    Advanced Material: Implementing Cache Controllers

    SystemVerilog

  3. mdu mdu Public

    Forked from zeeshanrafique23/mdu

    M-extension for RISC-V cores.

    Verilog

  4. schoolRISCV schoolRISCV Public

    Forked from zhelnio/schoolRISCV

    CPU microarchitecture, step by step

    Makefile 1

  5. schoolRISCV_ICache schoolRISCV_ICache Public

    Академический проект для исследования прироста производительности процессора в зависимости от конфигурации Иерархии Памяти

    Makefile 6 3