add licheerv

NobuoTsukamoto · Jun 30, 2022 · 9083c70 · 9083c70
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diff --git a/conf/machine/licheerv.conf b/conf/machine/licheerv.conf
@@ -0,0 +1,70 @@
+#@TYPE: Machine
+#@NAME: licheerv
+#@SOC:  Sipeed Lichee RV
+#@DESCRIPTION: Machine configuration for  Sipeed Lichee RV
+
+require conf/machine/include/riscv/tune-riscv.inc
+
+MACHINE_FEATURES = "screen keyboard ext2 ext3 serial"
+
+KERNEL_CLASSES = "kernel-fitimage"
+KERNEL_IMAGETYPE = "fitImage"
+UBOOT_ENV ?= "boot"
+UBOOT_ENV_SUFFIX = "scr.uimg"
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-licheerv-dev"
+PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-licheerv"
+
+PREFERRED_VERSION_openocd-native = "riscv"
+PREFERRED_VERSION_openocd = "riscv"
+
+EXTRA_IMAGEDEPENDS += "opensbi"
+RISCV_SBI_PLAT = "generic"
+
+## This sets u-boot as the default OpenSBI payload
+### Nezha board uses TOC1 images loaded by SPL and containing U-Boot, DTB, and
+### OpenSBI so 'RISCV_SBI_PAYLOAD' isn't used.
+### 'RISCV_SBI_FDT' isn't used because the DTB is loaded from RAM at
+### ${fdtcontroladdr}
+#RISCV_SBI_PAYLOAD ?= "u-boot.bin"
+#RISCV_SBI_FDT ?= "sun20i-d1-nezha.dtb"
+
+SERIAL_CONSOLES = "115200;ttyS0"
+
+MACHINE_EXTRA_RRECOMMENDS += " kernel-modules"
+
+IMAGE_FSTYPES += "wic.gz wic.bmap ext4"
+
+### 'KERNEL_DEVICETREE' isn't used because the DTB is loaded from RAM
+### at address ${fdtcontroladdr}
+#KERNEL_DEVICETREE ?= "allwinner/sun20i-d1-nezha.dtb"
+
+## Do not update fstab file when using wic images
+WIC_CREATE_EXTRA_ARGS ?= "--no-fstab-update"
+
+EXTRA_IMAGEDEPENDS += "u-boot-licheerv"
+UBOOT_MACHINE = "nezha_defconfig"
+
+
+UBOOT_ENTRYPOINT = "0x40200000"
+UBOOT_DTB_LOADADDRESS = "0x4FA00000"
+UBOOT_DTB = "1"
+UBOOT_DTB_BINARY ?= "sun20i-d1-lichee-rv-dock.dtb"
+
+# Deploy boot0 which is used as SPL
+EXTRA_IMAGEDEPENDS += "boot0"
+
+## wic default support
+WKS_FILE_DEPENDS ?= " \
+    u-boot-licheerv \
+    opensbi \
+    e2fsprogs-native \
+    bmap-tools-native \
+"
+
+IMAGE_BOOT_FILES ?= " \
+    ${KERNEL_IMAGETYPE} \
+    boot.scr.uimg \
+    uEnv.txt \
+"
+
+WKS_FILE ?= "licheerv.wks"
diff --git a/recipes-bsp/boot0/boot0.bb b/recipes-bsp/boot0/boot0.bb
@@ -30,4 +30,4 @@ do_deploy() {
 
 addtask deploy before do_build after do_compile
 
-COMPATIBLE_MACHINE = "nezha-allwinner-d1"
+COMPATIBLE_MACHINE = "nezha-allwinner-d1|licheerv"
diff --git a/recipes-bsp/opensbi/opensbi_%.bbappend b/recipes-bsp/opensbi/opensbi_%.bbappend
@@ -1,10 +1,16 @@
 # Mainline OpenSBI supports the C906 out of the box, but it needs a few tweaks
 # and a new reset driver for the sunxi watchdog.
 FILESEXTRAPATHS:prepend:nezha := "${THISDIR}/files:"
+FILESEXTRAPATHS:prepend:licheerv := "${THISDIR}/files:"
 
 SRC_URI:append:nezha = " \
     file://0001-lib-utils-fdt-Require-match-data-to-be-const.patch \
     file://0002-lib-utils-timer-Add-a-separate-compatible-for-the-D1.patch \
 "
+SRC_URI:append:licheerv = " \
+    file://0001-lib-utils-fdt-Require-match-data-to-be-const.patch \
+    file://0002-lib-utils-timer-Add-a-separate-compatible-for-the-D1.patch \
+"
 
 INSANE_SKIP:${PN}:nezha += "ldflags"
+INSANE_SKIP:${PN}:licheerv += "ldflags"
diff --git a/recipes-bsp/u-boot/u-boot-licheerv.bb b/recipes-bsp/u-boot/u-boot-licheerv.bb
@@ -0,0 +1,50 @@
+require recipes-bsp/u-boot/u-boot-common.inc
+require recipes-bsp/u-boot/u-boot.inc
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
+FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
+
+LIC_FILES_CHKSUM = "file://Licenses/README;md5=2ca5f2c35c8cc335f0a19756634782f1"
+
+SRC_URI = " \
+    git://github.com/smaeul/u-boot.git;protocol=https;branch=d1-wip \
+    file://0001-riscv-fix-build-with-binutils-2.38.patch \
+    file://tftp-mmc-boot.txt \
+    file://uEnv-licheerv.txt \
+    file://toc.cfg \
+"
+
+SRCREV = "afc07cec423f17ebb4448a19435292ddacf19c9b"
+
+DEPENDS:append = " u-boot-tools-native python3-setuptools-native"
+
+# Overwrite this for your server
+TFTP_SERVER_IP ?= "127.0.0.1"
+
+do_make_toc1_image[depends] = "opensbi:do_deploy"
+
+do_configure:prepend() {
+    sed -i -e 's,@SERVERIP@,${TFTP_SERVER_IP},g' ${WORKDIR}/tftp-mmc-boot.txt
+    mkimage -O linux -T script -C none -n "U-Boot boot script" \
+        -d ${WORKDIR}/tftp-mmc-boot.txt ${WORKDIR}/${UBOOT_ENV_BINARY}
+}
+
+# boot0 expects to load a TOC1 image containing OpenSBI and U-Boot
+# (and a DTB). This is similar to, but incompatible with, mainline U-Boot
+# SPL, which expects a FIT image.
+do_make_toc1_image() {
+    cd ${B}
+    cp ${DEPLOY_DIR_IMAGE}/fw_dynamic.bin ${B}
+    ${B}/tools/mkimage -T sunxi_toc1 -d ${WORKDIR}/toc.cfg ${B}/u-boot.toc1
+}
+
+do_deploy:append() {
+    install -m 644 ${B}/u-boot.toc1 ${DEPLOYDIR}
+    install -m 644 ${WORKDIR}/uEnv-licheerv.txt ${DEPLOYDIR}/uEnv.txt
+}
+
+COMPATIBLE_MACHINE = "(licheerv)"
+
+TOOLCHAIN = "gcc"
+
+addtask do_make_toc1_image before do_deploy after do_compile
diff --git a/recipes-bsp/u-boot/u-boot-licheerv/0001-riscv-fix-build-with-binutils-2.38.patch b/recipes-bsp/u-boot/u-boot-licheerv/0001-riscv-fix-build-with-binutils-2.38.patch
@@ -0,0 +1,57 @@
+From eb6f18cc6ee4a3902c373c4bb505c7fcc3450615 Mon Sep 17 00:00:00 2001
+From: Cezary Sobczak <cezary.sobczak@3mdeb.com>
+Date: Thu, 24 Mar 2022 00:23:14 +0100
+Subject: [PATCH] riscv: fix build with binutils 2.38
+
+Original patch:
+https://lore.kernel.org/all/YhCvlHomlT2js3uO@ubuntu01/T/
+
+From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei.
+
+The fix is to specify those extensions explicitely in -march. However as
+older binutils version do not support this, we first need to detect
+that.
+
+Fixes:
+| cache.c: Assembler messages:
+| cache.c:12: Error: unrecognized opcode `fence.i'
+| arch/riscv/cpu/mtrap.S: Assembler messages:
+| arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
+| arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
+| arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
+| arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
+
+Signed-off-by: Cezary Sobczak <cezary.sobczak@3mdeb.com>
+---
+ arch/riscv/Makefile | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 0b80eb8d8645..6b3dc6e514d8 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -24,8 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ 	CMODEL = medany
+ endif
+
+-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+-	     -mcmodel=$(CMODEL)
++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
++ifeq ($(toolchain-need-zicsr-zifencei),y)
++	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
++endif
++
++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) -mcmodel=$(CMODEL)
+
+ PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)
+ CFLAGS_EFI		+= $(ARCH_FLAGS)
+-- 
+2.25.1
+
diff --git a/recipes-bsp/u-boot/u-boot-licheerv/toc.cfg b/recipes-bsp/u-boot/u-boot-licheerv/toc.cfg
@@ -0,0 +1,9 @@
+[opensbi]
+file = fw_dynamic.bin
+addr = 0x40000000
+[dtb]
+file = u-boot.dtb
+addr = 0x44000000
+[u-boot]
+file = u-boot.bin
+addr = 0x4a000000
diff --git a/recipes-bsp/u-boot/u-boot-licheerv/uEnv-licheerv.txt b/recipes-bsp/u-boot/u-boot-licheerv/uEnv-licheerv.txt
@@ -0,0 +1,4 @@
+bootargs=earlycon=sbi clk_ignore_unused initcall_debug=0 console=ttyS0,115200 loglevel=8 root=/dev/mmcblk0p2 rootwait  init=/sbin/init
+bootcmd_load_f=load ${devtype} ${devnum}:${distro_bootpart} ${ramdisk_addr_r} fitImage
+bootcmd_run=bootm ${ramdisk_addr_r} - ${fdtcontroladdr}
+bootcmd=run bootcmd_load_f; run bootcmd_run
diff --git a/recipes-kernel/linux/linux-licheerv-dev.bb b/recipes-kernel/linux/linux-licheerv-dev.bb
@@ -0,0 +1,29 @@
+require recipes-kernel/linux/linux-mainline-common.inc
+FILESEXTRAPATHS:prepend = "${FILE_DIRNAME}/linux-licheerv:"
+SUMMARY = "Nezha dev kernel recipe"
+
+SRCREV_meta ?= "ea948a0983d7b7820814e5bce4eda3079201bd95"
+SRCREV_machine ?= "fe178cf0153d98b71cb01a46c8cc050826a17e77"
+FORK ?= "smaeul"
+BRANCH ?= "riscv/d1-wip"
+KMETA = "kernel-meta"
+
+# It is necessary to add to SRC_URI link to the 'yocto-kernel-cache' due to
+# override of the original SRC_URI:
+# "do_kernel_metadata: Check the SRC_URI for meta-data repositories or
+# directories that may be missing"
+SRC_URI = " \
+        git://github.com/${FORK}/linux.git;name=machine;protocol=https;branch=${BRANCH} \
+        git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-5.15;destsuffix=${KMETA} \
+        file://licheerv_linux_defconfig \
+    "
+
+LINUX_VERSION ?= "5.19-rc1"
+LINUX_VERSION_EXTENSION:append = "-licheerv"
+
+KERNEL_FEATURES += "features/cgroups/cgroups.cfg"
+KERNEL_FEATURES += "ktypes/standard/standard.cfg"
+
+KCONFIG_MODE = "licheerv_linux_defconfig"
+
+COMPATIBLE_MACHINE = "(licheerv)"
diff --git a/recipes-kernel/linux/linux-licheerv/0001-riscv-fix-build-with-binutils-2.38.patch b/recipes-kernel/linux/linux-licheerv/0001-riscv-fix-build-with-binutils-2.38.patch
@@ -0,0 +1,55 @@
+From 46602fe7729b285a823a1bab49d5f77e643be021 Mon Sep 17 00:00:00 2001
+From: Cezary Sobczak <cezary.sobczak@3mdeb.com>
+Date: Wed, 23 Mar 2022 23:34:37 +0100
+Subject: [PATCH] riscv: fix build with binutils 2.38
+
+Original source of this patch:
+- https://lore.kernel.org/lkml/YgVRu9Z0BDyJdjR5@kroah.com/T/
+
+From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei. As the kernel uses those instruction,
+this causes the following build failure:
+
+  CC      arch/riscv/kernel/vdso/vgettimeofday.o
+  <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
+  <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
+  <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
+  <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
+  <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
+
+The fix is to specify those extensions explicitely in -march. However as
+older binutils version do not support this, we first need to detect
+that.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Cezary Sobczak <cezary.sobczak@3mdeb.com>
+---
+ arch/riscv/Makefile | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 8a107ed18b0d..7d81102cffd4 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
+ riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
+ riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
+ riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
++riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
++
+ KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
+ KBUILD_AFLAGS += -march=$(riscv-march-y)
+
+-- 
+2.25.1
+