OpenEmbedded/Yocto layer for RISC-V Architecture
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pino-kim and kraj qemu : Usermode fails with invalid instruction error (for riscv32)
- backport for riscv32 arch
- Usermode fails with invalid instruction error (for riscv32)

Signed-off-by: pino-kim <>
Latest commit 7a3af75 Dec 11, 2018


RISC-V Architecture Layer for OpenEmbedded/Yocto

license Build Status


This is the general hardware specific BSP overlay for the RISC-V based devices.

More information can be found at: (Official Site)

The core BSP part of meta-riscv should work with different OpenEmbedded/Yocto distributions and layer stacks, such as:

  • Distro-less (only with OE-Core).
  • Angstrom.
  • Yocto/Poky (main focus of testing).


This layer depends on:

  • URI: git://
    • branch: master
    • revision: HEAD
  • URI: git://
    • branch: master
    • revision: HEAD

Quick Start

Note: You only need this if you do not have an existing Yocto Project build environment.

Make sure to install the repo command by Google first.

Create workspace

mkdir riscv-yocto && cd riscv-yocto
repo init -u git://  -b master -m tools/manifests/riscv-yocto.xml
repo sync
repo start work --all

Update existing workspace

In order to bring all layers uptodate with upstream

cd riscv-yocto
repo sync
repo rebase

Setup Build Environment

. ./meta-riscv/

Build Image

A console-only image

bitbake core-image-full-cmdline

Basic image without X support suitable for Linux Standard Base (LSB) implementations. It includes the full meta-toolchain, plus development headers and libraries to form a standalone (on device) SDK

bitbake core-image-lsb-sdk

Run in QEMU

runqemu nographic

Running wic.gz image on hardware

The output of the build will be a <image>.wic.gz file. You can write this file to an sd card using:

$ zcat <image>-<machine>.wic.gz | sudo dd of=/dev/sdX bs=4M iflag=fullblock oflag=direct conv=fsync status=progress


  • Khem Raj <raj dot khem at>