Skip to content
View Noris4est's full-sized avatar
6 followers · 4 following
Block or Report

Block or report Noris4est

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories

  1. I2C-FPGA-Verilog-HDL I2C-FPGA-Verilog-HDL Public

    In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardware description language.

    Verilog 10 3

  2. SPI-FPGA-Verilog-HDL SPI-FPGA-Verilog-HDL Public

    In this project, I am developing a verilog SPI interface for FPGA

    Verilog 2

  3. UART-FPGA-Verilog-HDL UART-FPGA-Verilog-HDL Public

    In this project, I am developing an interface for the FPGA platform that implements the UART protocol. Hardware description language selected by Verilog

    Verilog 1

  4. PWM-FPGA-VERILOG PWM-FPGA-VERILOG Public

    I am developing a PWM parametric module.

    Verilog 1

  5. Pulse-shortening-device-FPGA-VERILOG-HDL Pulse-shortening-device-FPGA-VERILOG-HDL Public

    In this project, I am developing a signal shortener (single-osc).

    Verilog 1

  6. RISE_EDGE_PULSE_LENGTH_CONVERTER RISE_EDGE_PULSE_LENGTH_CONVERTER Public

    Here I am developing a pulse length converter

    Verilog 1