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if { $modelsim == 1 } { | ||
if { [info exists wlan_path ] } { | ||
set here $wlan_path | ||
} else { | ||
set here "" | ||
} | ||
} else { | ||
set here $::quartus(qip_path) | ||
} | ||
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set wlan_common [list \ | ||
[file normalize [ file join $here ../vhdl/wlan_p.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_tx_p.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_rx_p.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_interleaver_p.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_lfsr.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/clock_sync_logic.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/clock_sync_params.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/clock_sync_logic_vector.vhd] ] \ | ||
] ; | ||
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set wlan_synthesis_tx [list \ | ||
[file normalize [ file join $here ../vhdl/wlan_descrambler.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_viterbi_encoder.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_scrambler.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_crc.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_framer.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_encoder.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_modulator.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_interleaver.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_ifft64.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_tx_short.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_tx_long.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_tx_controller.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_sample_buffer.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_symbol_shaper.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_tx.vhd] ] \ | ||
] ; | ||
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set wlan_synthesis_rx [ list \ | ||
[file normalize [ file join $here ../ip/nuand/cordic.vhd] ] \ | ||
[file normalize [ file join $here ../ip/nuand/nco.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_agc.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_agc_drv.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_dsss_despreader.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_dsss_plcp_crc.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_dsss_p_norm.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_dsss_demodulator.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_dsss_peak_finder.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_dsss_rx_controller.vhd] ]\ | ||
[file normalize [ file join $here ../vhdl/wlan_dsss_rx_framer.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_dsss_rx.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_divide.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_channel_inverter.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_clamper.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_crc.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_rx_packet_buffer.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_rx_framer.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_csma.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_bsd.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_clamper.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_viterbi_decoder.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_depuncturer.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_deinterleaver.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_phase_correction.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_demodulator.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_equalizer.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_fft64.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_rx_controller.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_cfo_correction.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_cfo_estimate.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_peak_finder.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_delay_correlator.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_correlator.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_p_norm.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_acquisition.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_rx.vhd] ] \ | ||
] ; | ||
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set wlan_synthesis_top [ list \ | ||
[file normalize [ file join $here ../vhdl/wlan_ack_generator.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_dcf.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/wlan_top.vhd] ] \ | ||
] ; | ||
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set wlan_sim [ list \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_clock_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_viterbi_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_dsss_plcp_crc_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_sample_loader.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_sample_saver.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_tables_p.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_peak_finder_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_symbol_shaper_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_viterbi_encoder_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_lfsr_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_modulator_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_interleaver_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_tx_short_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_tx_long_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_ack_generator_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_acquisition_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_tx_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_rx_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_top_tb.vhd] ] \ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_channel_inverter_tb.vhd] ]\ | ||
[file normalize [ file join $here ../vhdl/tb/wlan_tb.vhd] ] \ | ||
] ; | ||
|
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-- This file is part of bladeRF-wiphy. | ||
-- | ||
-- Copyright (C) 2020 Nuand, LLC. | ||
-- | ||
-- This program is free software; you can redistribute it and/or modify | ||
-- it under the terms of the GNU General Public License as published by | ||
-- the Free Software Foundation; either version 2 of the License, or | ||
-- (at your option) any later version. | ||
-- | ||
-- This program is distributed in the hope that it will be useful, | ||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
-- GNU General Public License for more details. | ||
-- | ||
-- You should have received a copy of the GNU General Public License along | ||
-- with this program; if not, write to the Free Software Foundation, Inc., | ||
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
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library ieee ; | ||
use ieee.std_logic_1164.all ; | ||
use ieee.numeric_std.all ; | ||
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package cordic_p is | ||
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-- Vectoring mode forces outputs.y to 0 | ||
-- Rotation mode forces outputs.z to 0 | ||
type cordic_mode_t is (CORDIC_ROTATION, CORDIC_VECTORING) ; | ||
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-- TODO: Make this a generic package | ||
type cordic_xyz_t is record | ||
x : signed(15 downto 0) ; | ||
y : signed(15 downto 0) ; | ||
z : signed(15 downto 0) ; | ||
valid : std_logic ; | ||
end record ; | ||
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end package ; -- cordic_p | ||
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library ieee ; | ||
use ieee.std_logic_1164.all ; | ||
use ieee.numeric_std.all ; | ||
use ieee.math_real.all ; | ||
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library work ; | ||
use work.cordic_p.all ; | ||
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entity cordic is | ||
port ( | ||
clock : in std_logic ; | ||
reset : in std_logic ; | ||
mode : in cordic_mode_t ; | ||
inputs : in cordic_xyz_t ; | ||
normalized : out cordic_xyz_t ; | ||
outputs : out cordic_xyz_t | ||
) ; | ||
end entity ; -- cordic | ||
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architecture arch of cordic is | ||
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-- TODO: Make this generic | ||
constant NUM_STAGES : natural := 14 ; | ||
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-- TODO: Use the VHDL-2008 integer_vector | ||
type integer_array_t is array(natural range <>) of integer ; | ||
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-- Each stage of the CORDIC is atan(2^(-i)) | ||
function calculate_cordic_table return integer_array_t is | ||
variable rv : integer_array_t(0 to NUM_STAGES-1) := (others => 0) ; | ||
begin | ||
for i in 0 to rv'high loop | ||
rv(i) := integer(round((2.0**NUM_STAGES)*arctan(2.0**(-i))/MATH_PI)) ; | ||
end loop ; | ||
return rv ; | ||
end function ; | ||
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-- Constant array | ||
constant K : integer_array_t := calculate_cordic_table ; | ||
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-- The array for CORDIC stages | ||
type xyzs_t is array(0 to NUM_STAGES-1) of cordic_xyz_t ; | ||
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-- ALl the XYZ's for the CORDIC stages | ||
signal xyzs : xyzs_t ; | ||
signal nxyzs : xyzs_t ; | ||
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signal nflip : std_logic_vector(0 to NUM_STAGES-1) ; | ||
begin | ||
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rotate : process(clock, reset) | ||
begin | ||
if( reset = '1' ) then | ||
xyzs <= (others =>(x => (others =>'0'), y => (others =>'0'), z => (others =>'0'), valid => '0')) ; | ||
nxyzs <= (others =>(x => (others =>'0'), y => (others =>'0'), z => (others =>'0'), valid => '0')) ; | ||
nflip <= (others => '0') ; | ||
elsif( rising_edge( clock ) ) then | ||
-- First stage will rotate the vector to be within -pi/2 to pi/2 | ||
xyzs(0).valid <= inputs.valid ; | ||
nxyzs(0).valid <= inputs.valid ; | ||
if( inputs.valid = '1' ) then | ||
case mode is | ||
when CORDIC_ROTATION => | ||
-- Make sure we're only rotating -pi/2 to pi/2 and adjust accordingly | ||
if( inputs.z > 2**(NUM_STAGES-1) ) then | ||
xyzs(0).x <= -inputs.x ; | ||
xyzs(0).y <= -inputs.y ; | ||
xyzs(0).z <= inputs.z - 2**NUM_STAGES ; | ||
elsif( inputs.z < -(2**(NUM_STAGES-1)) ) then | ||
xyzs(0).x <= -inputs.x ; | ||
xyzs(0).y <= -inputs.y ; | ||
xyzs(0).z <= inputs.z + 2**NUM_STAGES ; | ||
else | ||
xyzs(0).x <= inputs.x ; | ||
xyzs(0).y <= inputs.y ; | ||
xyzs(0).z <= inputs.z ; | ||
end if ; | ||
when CORDIC_VECTORING => | ||
nxyzs(0).x <= to_signed(1243, nxyzs(0).x'length) ; | ||
nxyzs(0).y <= (others => '0') ; | ||
nflip(0) <= '1' ; | ||
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-- Make sure we're in the 1st or 4th quadrant only | ||
if( inputs.x < 0 and inputs.y < 0 ) then | ||
xyzs(0).x <= -inputs.x ; | ||
xyzs(0).y <= -inputs.y ; | ||
xyzs(0).z <= inputs.z - 2**(NUM_STAGES) ; | ||
elsif( inputs.x < 0 ) then | ||
xyzs(0).x <= -inputs.x ; | ||
xyzs(0).y <= -inputs.y ; | ||
xyzs(0).z <= inputs.z + 2**(NUM_STAGES) ; | ||
else | ||
xyzs(0).x <= inputs.x ; | ||
xyzs(0).y <= inputs.y ; | ||
xyzs(0).z <= inputs.z ; | ||
nflip(0) <= '0' ; | ||
end if ; | ||
end case ; | ||
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end if ; | ||
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-- Run through all the other stages | ||
for i in 0 to xyzs'high-1 loop | ||
xyzs(i+1).valid <= xyzs(i).valid ; | ||
nxyzs(i+1).valid <= nxyzs(i).valid ; | ||
nflip(i+1) <= nflip(i) ; | ||
if( xyzs(i).valid = '1' ) then | ||
case mode is | ||
when CORDIC_ROTATION => | ||
if( xyzs(i).z < 0 ) then | ||
xyzs(i+1).x <= xyzs(i).x + shift_right(xyzs(i).y, i) ; | ||
xyzs(i+1).y <= xyzs(i).y - shift_right(xyzs(i).x, i) ; | ||
xyzs(i+1).z <= xyzs(i).z + K(i) ; | ||
else | ||
xyzs(i+1).x <= xyzs(i).x - shift_right(xyzs(i).y, i) ; | ||
xyzs(i+1).y <= xyzs(i).y + shift_right(xyzs(i).x, i) ; | ||
xyzs(i+1).z <= xyzs(i).z - K(i) ; | ||
end if ; | ||
when CORDIC_VECTORING => | ||
if( xyzs(i).y < 0 ) then | ||
xyzs(i+1).x <= xyzs(i).x - shift_right(xyzs(i).y, i) ; | ||
xyzs(i+1).y <= xyzs(i).y + shift_right(xyzs(i).x, i) ; | ||
xyzs(i+1).z <= xyzs(i).z - K(i) ; | ||
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nxyzs(i+1).x <= nxyzs(i).x + shift_right(nxyzs(i).y, i) ; | ||
nxyzs(i+1).y <= nxyzs(i).y - shift_right(nxyzs(i).x, i) ; | ||
else | ||
xyzs(i+1).x <= xyzs(i).x + shift_right(xyzs(i).y, i) ; | ||
xyzs(i+1).y <= xyzs(i).y - shift_right(xyzs(i).x, i) ; | ||
xyzs(i+1).z <= xyzs(i).z + K(i) ; | ||
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nxyzs(i+1).x <= nxyzs(i).x - shift_right(nxyzs(i).y, i) ; | ||
nxyzs(i+1).y <= nxyzs(i).y + shift_right(nxyzs(i).x, i) ; | ||
end if ; | ||
end case ; | ||
end if ; | ||
end loop ; | ||
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-- Output stage | ||
outputs <= xyzs(xyzs'high) ; | ||
end if ; | ||
end process ; | ||
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normalized_output : process(clock, reset) | ||
begin | ||
if( reset = '1' ) then | ||
normalized <= (x => (others =>'0'), y => (others =>'0'), z => (others =>'0'), valid => '0') ; | ||
elsif( rising_edge( clock ) ) then | ||
normalized.valid <= '0' ; | ||
if( nxyzs(nxyzs'high).valid = '1' ) then | ||
if( nflip(nflip'high) = '1' ) then | ||
normalized.x <= - nxyzs(nxyzs'high).x ; | ||
normalized.y <= - nxyzs(nxyzs'high).y ; | ||
else | ||
normalized.x <= nxyzs(nxyzs'high).x ; | ||
normalized.y <= nxyzs(nxyzs'high).y ; | ||
end if ; | ||
normalized.valid <= '1' ; | ||
end if ; | ||
end if ; | ||
end process ; | ||
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end architecture ; -- arch |
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