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[libbladeRF] RXVGA2 DC autocalibration intermittently returns 31 for all values #269

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jynik opened this Issue Jul 3, 2014 · 3 comments

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jynik commented Jul 3, 2014

I'm seeing this occur on some boards, but not others. (However, I only have a very small sample size).

Currently, I'm digging into this and looking to query the Lime folks on their Google group for more info.

@jynik jynik added this to the 2014.09-rc2 milestone Jul 3, 2014

@jynik jynik self-assigned this Jul 3, 2014

@jynik jynik changed the title from [libbladeRF] RXVGA2 DC autocalibration sometimes returns 31 for all values to [libbladeRF] RXVGA2 DC autocalibration intermittently returns 31 for all values Jul 3, 2014

@jynik jynik added the bug label Jul 27, 2014

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jynik Aug 3, 2014

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While terribly inconvenient, one workaround is to rerun cal dc lms until it stops returning 31's. This generally seems to yield some usable values, but may intermittently cause the LMS to go out to lunch.

I've been swamped with a few other tasks, but will be getting back to this soon.

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jynik commented Aug 3, 2014

While terribly inconvenient, one workaround is to rerun cal dc lms until it stops returning 31's. This generally seems to yield some usable values, but may intermittently cause the LMS to go out to lunch.

I've been swamped with a few other tasks, but will be getting back to this soon.

@jynik jynik modified the milestones: 2014.09-rc3, 2014.09 Aug 18, 2014

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jynik Oct 21, 2014

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I've verified this to be a timing issue in the FPGA by comparing transactions on the SPI bus to what the NIOS sees. @bpadalino is hot on the trail.

A temporary workaround is to slow down the LMS SPI bus clock rate. 5 MHz was rock solid for me.

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jynik commented Oct 21, 2014

I've verified this to be a timing issue in the FPGA by comparing transactions on the SPI bus to what the NIOS sees. @bpadalino is hot on the trail.

A temporary workaround is to slow down the LMS SPI bus clock rate. 5 MHz was rock solid for me.

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jynik Oct 22, 2014

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Addressed by FPGA v0.1.1 (9c0bbfe)

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jynik commented Oct 22, 2014

Addressed by FPGA v0.1.1 (9c0bbfe)

@jynik jynik closed this Oct 22, 2014

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