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fix: set FPGA buffer read only for bias mode device bias.
- Set Host and FPGA buffer map Writable for Host BIAS mode targeting Host address and Host BIAS mode targeting HDM (Device) address - Set FPGA buffer map read-only for device BIAS mode targeting HDM (Device) address CXL Driver IOCTL buffer map by default Read-only flag value is 0, Set buffer map flag to DFL_CXL_BUFFER_MAP for Read/write buffers struct dfl_cxl_cache_buffer_map { __u32 argsz; #define DFL_CXL_BUFFER_MAP_WRITABLE 1 __u32 flags; __u64 user_addr; __u64 length; } Signed-off-by: anandaravuri <ananda.ravuri@intel.com>
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