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opaec++: update doxygen for the current classes #140

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merged 4 commits into from
Jan 8, 2018

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tswhison
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@tswhison tswhison commented Jan 5, 2018

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@tswhison tswhison self-assigned this Jan 5, 2018
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Pretty good 😀
Just a few comments and I'm wondering if we should be a little more generic and not refer to accelerators as much but instead refer to fpga resources. Thoughts?

@@ -36,14 +36,26 @@ namespace opae {
namespace fpga {
namespace types {

/** An allocated accelerator
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Should we use accelerator or something more generic like fpga resource?
A handle can represent either logical accelerator object or a physical fpga object.
In other words, can a fpgaconf be rewritten to use this C++ API (upper layer included) and if so, what would it look like?

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Hmm.. I was purposefully staying away from fpga so that we didn't limit ourselves. How about "accelerator resource"?

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Limit ourselves to just FPGA SW? The namespace already includes fpga...

*
* properties are information describing an
* accelerator resource that is identified by
* its token.
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Should we add something about properties also being used as a query for enumeration?

operator fpga_properties() const { return props_; }

/** Retrieve the properties for a given token object.
* @param[in] t A token identifying the accelerator resource.
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Similar comment to a previous one. Should we use something more generic like fpga resource?

@@ -37,16 +37,30 @@ namespace opae {
namespace fpga {
namespace types {

/** Wraps the OPAE fpga_token primitive.
* token's are enumerated based on a set of
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There's an apostrophe in tokens. What about changing this to read something like:
tokens are created from an enumeration operation that uses properties describing an fpga resource

*
* Represents an accelerator resource that has
* been allocated by OPAE. The accelerator's
* MMIO regions are made available for reading
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Hmm. MMIO is implementation for register access. If you want to keep things generic, maybe you could rephrase this part:

Depending on the type of resource, its registers space may be read/written using a handle object.

We may also think about this too for the documentation for the read/write functions.

@@ -80,9 +91,29 @@ class handle {
*/
uint8_t *mmio_ptr(uint64_t offset) const { return mmio_base_ + offset; }

/** Allocate an accelerator, given a raw fpga_token
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Allocate or Open? Also, should we use "accelerator resource"?

@tswhison tswhison merged commit 222f780 into feature/c++ Jan 8, 2018
@tswhison tswhison deleted the tswhison/doxygen branch January 8, 2018 23:02
tswhison pushed a commit that referenced this pull request Mar 12, 2020
* opae.admin: Add virtualization APIs

* Cleanup sriov related attributes/methods
* Move port assing/release into fme class
* Fix region.ioctl method
  * remove mutate_flag from ioctl call
  * default mode to 'w'
  * tested/works on both Python 2.7 and Python 3.6
* refactor fpgaport

* opae.admin: sriov: change code per suggestion
tswhison pushed a commit that referenced this pull request Mar 13, 2020
* opae.admin: Add virtualization APIs

* Cleanup sriov related attributes/methods
* Move port assing/release into fme class
* Fix region.ioctl method
  * remove mutate_flag from ioctl call
  * default mode to 'w'
  * tested/works on both Python 2.7 and Python 3.6
* refactor fpgaport

* opae.admin: sriov: change code per suggestion
r-rojo pushed a commit that referenced this pull request Mar 12, 2021
a53e62e ofs-umd: fix ofs_add_driver cmake macro (#140)
59ec00f libofs: add libofs and umd (user mode driver) framework
9561585 libofs: fix blank lines in files
b75690c libofs: finish migration to opae-libs repo
f552e4d ofs_parse: look for call nodes in ast
049e00a ofs-umd: fix ofs_resolve to check func.id
4006206 libofs: add macros to wait for bit fields
15bac6c ofs umd: add ofs umd framework (#1909)
e62592b ofs: initial implementation of libofs (#1899)

git-subtree-dir: opae-libs
git-subtree-split: a53e62e
r-rojo added a commit that referenced this pull request Oct 11, 2021
Use OPAE_LIBS_ROOT when referencing dependancy ofs_parse.py

Signed-off-by: Rodrigo Rojo <rodrigo.rojo@intel.com>
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2 participants