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fix:CXL traffic generator read/write bandwidth and input arguments bou… #3054

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merged 3 commits into from
Dec 1, 2023

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anandaravuri
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…ndary check

fix#1
For the correct value of loop count, the following condition must be satisfied. max(READ,WRITE) * loop_count <= 268,435,456

fix #2
cannot have READs only (without any previous WRITEs)

fix #3
READs cannot exceed #WRITEs

Fix #4
Read HDM size from CSR.

…ndary check

fix#1
For the correct value of loop count, the following condition must be satisfied.
max(READ,WRITE) * loop_count <= 268,435,456

fix #2
cannot have READs only (without any previous WRITEs)

fix #3
 READs cannot exceed #WRITEs

Fix #4
Read HDM size from CSR.

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>
@anandaravuri anandaravuri requested a review from a team as a code owner November 30, 2023 23:44
samples/cxl_mem_tg/cxl_tg_test.h Outdated Show resolved Hide resolved
samples/cxl_mem_tg/cxl_tg_test.h Outdated Show resolved Hide resolved
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coveralls commented Nov 30, 2023

Pull Request Test Coverage Report for Build 7062844447

  • 0 of 26 (0.0%) changed or added relevant lines in 2 files are covered.
  • 1 unchanged line in 1 file lost coverage.
  • Overall coverage decreased (-0.07%) to 67.551%

Changes Missing Coverage Covered Lines Changed/Added Lines %
samples/cxl_mem_tg/cxl_mem_tg.h 0 2 0.0%
samples/cxl_mem_tg/cxl_tg_test.h 0 24 0.0%
Files with Coverage Reduction New Missed Lines %
samples/cxl_mem_tg/cxl_tg_test.h 1 0.0%
Totals Coverage Status
Change from base Build 7052608277: -0.07%
Covered Lines: 15755
Relevant Lines: 23323

💛 - Coveralls

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>
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👍

@anandaravuri anandaravuri merged commit 09a0e22 into master Dec 1, 2023
27 checks passed
@anandaravuri anandaravuri deleted the aravuri/fix_clx_tg_bw branch December 1, 2023 17:33
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about sample for hw?
3 participants