drivers: atmel_saic: add SAIC driver

Add a driver to handle interrupt that are targeting the secure
interrupt controller. This driver will be used to handle watchdog and
matrix interrupts.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

core/arch/arm/dts/sama5d2.dtsi

@@ -1024,6 +1024,16 @@
 				atmel,external-irqs = <49>;
 			};
 
+			saic: interrupt-controller@f803c000 {
+				#interrupt-cells = <3>;
+				compatible = "atmel,sama5d2-saic";
+				interrupt-controller;
+				reg = <0xf803c000 0x200>;
+				atmel,external-irqs = <49>;
+				status = "disabled";
+				secure-status = "okay";
+			};
+
 			i2c1: i2c@fc028000 {
 				compatible = "atmel,sama5d2-i2c";
 				reg = <0xfc028000 0x100>;

core/arch/arm/plat-sam/conf.mk

@@ -17,6 +17,7 @@ include core/arch/arm/cpu/cortex-a5.mk
 
 $(call force,CFG_TEE_CORE_NB_CORE,1)
 $(call force,CFG_ATMEL_UART,y)
+$(call force,CFG_ATMEL_SAIC,y)
 $(call force,CFG_SECURE_TIME_SOURCE_REE,y)
 $(call force,CFG_NO_SMP,y)
 $(call force,CFG_PL310,y)

core/arch/arm/plat-sam/sam_sfr.h

@@ -8,8 +8,16 @@
 
 #include <util.h>
 
+/* OHCI INT Configuration Register */
+#define AT91_SFR_OHCIICR	0x10
 /* UTMI Clock Trimming Register */
 #define AT91_SFR_UTMICKTRIM	0x30
+/* Serial number 0 Register */
+#define AT91_SFR_SN0		0x4c
+/* Serial number 1 Register */
+#define AT91_SFR_SN1		0x50
+/* AIC Interrupt Redirection Register */
+#define AT91_SFR_AICREDIR	0x54
 /* L2 cache RAM used as an internal SRAM */
 #define AT91_SFR_L2CC_HRAMC		0x58
 /* I2SC Register */
@@ -18,6 +26,9 @@
 /* Field definitions */
 #define AT91_UTMICKTRIM_FREQ			GENMASK_32(1, 0)
 
+#define AT91_SFR_AICREDIR_XOR_KEY		0xb6d81c4d
+#define AT91_SFR_AICREDIR_KEY_MASK		GENMASK_32(31, 1)
+
 vaddr_t sam_sfr_base(void);
 
 #endif