arm: pl310: fix cache sync

According to PL310 TRM:
Atomic operations:
The following are atomic operations:
    Clean Line by PA or by Set/Way
    Invalidate Line by PA
    Clean and Invalidate Line by PA or by Set/Way
    Cache Sync.
These operations stall the slave ports until they are complete.
When these registers are read, bit [0], the C flag, indicates that
a background operation is in progress. When written, bit 0 must be
zero.

So write 1 to sync register is not correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

core/arch/arm/kernel/tz_ssvce_pl310_a32.S

@@ -96,7 +96,7 @@ loop_cli_sync:
 	cmp	r1, #0
 	bne	loop_cli_sync
 
-	mov	r1, #1
+	mov	r1, #0
 	str	r1, [r0, #PL310_SYNC]
 
 loop_cli_sync_done:
@@ -126,7 +126,7 @@ loop_inv_way_sync:
 	cmp	r1, #0
 	bne	loop_inv_way_sync
 
-	mov	r1, #1
+	mov	r1, #0
 	str	r1, [r0, #PL310_SYNC]
 
 loop_inv_way_sync_done:
@@ -156,7 +156,7 @@ loop_cl_way_sync:
 	cmp	r1, #0
 	bne	loop_cl_way_sync
 
-	mov	r1, #1
+	mov	r1, #0
 	str	r1, [r0, #PL310_SYNC]
 
 loop_cl_way_sync_done:
@@ -211,7 +211,7 @@ loop_xxx_pa_sync:
 	cmp	r12, #0
 	bne	loop_xxx_pa_sync
 
-	mov	r12, #1
+	mov	r12, #0
 	str	r12, [r0, #PL310_SYNC]
 
 loop_xxx_pa_sync_done: