core: add tlbi_mva_range_asid()

Adds tlbi_mva_range_asid() which invalidates a range of virtual addresses for a specific ASID. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
OP-TEE · Feb 25, 2021 · c1e0a83 · c1e0a83
1 parent 3fb2048
commit c1e0a83
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Showing 3 changed files with 34 additions and 2 deletions.
diff --git a/core/arch/arm/include/kernel/tlb_helpers.h b/core/arch/arm/include/kernel/tlb_helpers.h
@@ -25,11 +25,10 @@ static inline void tlbi_mva_allasid_nosync(vaddr_t va)
 #endif
 }
 
-static inline void tlbi_mva_asid(vaddr_t va, uint32_t asid)
+static inline void tlbi_mva_asid_nosync(vaddr_t va, uint32_t asid)
 {
 	uint32_t a = asid & TLBI_ASID_MASK;
 
-	dsb_ishst();
 #ifdef ARM64
 	tlbi_vale1is((va >> TLBI_MVA_SHIFT) | SHIFT_U64(a, TLBI_ASID_SHIFT));
 	tlbi_vale1is((va >> TLBI_MVA_SHIFT) |
@@ -38,6 +37,12 @@ static inline void tlbi_mva_asid(vaddr_t va, uint32_t asid)
 	write_tlbimvais((va & ~(BIT32(TLBI_MVA_SHIFT) - 1)) | a);
 	write_tlbimvais((va & ~(BIT32(TLBI_MVA_SHIFT) - 1)) | a | 1);
 #endif
+}
+
+static inline void tlbi_mva_asid(vaddr_t va, uint32_t asid)
+{
+	dsb_ishst();
+	tlbi_mva_asid_nosync(va, asid);
 	dsb_ish();
 	isb();
 }

diff --git a/core/arch/arm/include/mm/core_mmu.h b/core/arch/arm/include/mm/core_mmu.h
@@ -628,6 +628,18 @@ bool core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, size_t len);
  */
 void tlbi_mva_range(vaddr_t va, size_t len, size_t granule);
 
+/*
+ * tlbi_mva_range_asid() - Invalidate TLB for virtual address range for
+ *			   a specific ASID
+ * @va:		start virtual address, must be a multiple of @granule
+ * @len:	length in bytes of range, must be a multiple of @granule
+ * @granule:	granularity of mapping, supported values are
+ *		CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must
+ *		match the actual mappings.
+ * @asid:	Address space identifier
+ */
+void tlbi_mva_range_asid(vaddr_t va, size_t len, size_t granule, uint32_t asid);
+
 /* Cache maintenance operation type */
 enum cache_op {
 	DCACHE_CLEAN,

diff --git a/core/arch/arm/mm/core_mmu.c b/core/arch/arm/mm/core_mmu.c
@@ -1374,6 +1374,21 @@ void tlbi_mva_range(vaddr_t va, size_t len, size_t granule)
 	isb();
 }
 
+void tlbi_mva_range_asid(vaddr_t va, size_t len, size_t granule, uint32_t asid)
+{
+	assert(granule == CORE_MMU_PGDIR_SIZE || granule == SMALL_PAGE_SIZE);
+	assert(!(va & (granule - 1)) && !(len & (granule - 1)));
+
+	dsb_ishst();
+	while (len) {
+		tlbi_mva_asid_nosync(va, asid);
+		len -= granule;
+		va += granule;
+	}
+	dsb_ish();
+	isb();
+}
+
 TEE_Result cache_op_inner(enum cache_op op, void *va, size_t len)
 {
 	switch (op) {