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Merge pull request #28 from imuguruza/alhambra_II
Add Alhambra II support to tutorials
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*.bin | ||
*.blif | ||
*.txt | ||
*.asc | ||
*.json |
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# README | ||
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Tutorial ports to [Alhambra II board](https://alhambrabits.com/alhambra/). Now using [nextpnr](https://github.com/YosysHQ/nextpnr) instead of `arachne`. | ||
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## Requisites | ||
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Apart from the tools described in the tutorials, you need to install `nextpnr`. Steps: | ||
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Install the dependencies: | ||
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```bash | ||
$ sudo apt install python3-dev | ||
$ sudo apt install libboost-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev libboost-python-dev libboost-iostreams-dev libboost-dev | ||
$ sudo apt install libeigen3-dev | ||
$ sudo apt install qt5-default | ||
``` | ||
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Now compile & install `nextpnr`: | ||
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```bash | ||
$ cmake -DARCH=ice40 . | ||
$ make -j$(nproc) | ||
$ sudo make install | ||
``` |
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#------------------------------------------------------- | ||
#-- Objetivo por defecto: hacer simulacion y sintesis | ||
#------------------------------------------------------- | ||
all: sim sint | ||
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#---------------------------------------------- | ||
#-- make sim | ||
#---------------------------------------------- | ||
#-- Objetivo para hacer la simulacion del | ||
#-- banco de pruebas | ||
#---------------------------------------------- | ||
sim: setbit_tb.vcd | ||
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#----------------------------------------------- | ||
#- make sint | ||
#----------------------------------------------- | ||
#- Objetivo para realizar la sintetis completa | ||
#- y dejar el diseno listo para su grabacion en | ||
#- la FPGA | ||
#----------------------------------------------- | ||
sint: setbit.bin | ||
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#------------------------------- | ||
#-- Compilacion y simulacion | ||
#------------------------------- | ||
setbit_tb.vcd: setbit.v setbit_tb.v | ||
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#-- Compilar | ||
iverilog -o setbit_tb.out setbit.v setbit_tb.v | ||
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#-- Simular | ||
./setbit_tb.out | ||
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#-- Ver visualmente la simulacion con gtkwave | ||
gtkwave setbit_tb.vcd setbit_tb.gtkw & | ||
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#------------------------------ | ||
#-- Sintesis completa | ||
#------------------------------ | ||
setbit.bin: setbit.v setbit.pcf | ||
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#-- Sintesis | ||
#OLD | ||
#yosys -p "synth_ice40 -blif setbit.blif" setbit.v | ||
yosys -p 'synth_ice40 -top setbit -json setbit.json' setbit.v | ||
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#-- Place & route | ||
#OLD | ||
#arachne-pnr -d 8k -P tq144:4k -p setbit.pcf setbit.blif -o setbit.txt | ||
#NEW - use nextpnr | ||
nextpnr-ice40 --hx8k --package tq144:4k --json setbit.json --pcf setbit.pcf --asc setbit.asc | ||
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#-- Generar binario final, listo para descargar en fgpa | ||
#OLD | ||
#icepack setbit.txt setbit.bin | ||
icepack setbit.asc setbit.bin | ||
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#------------------------------ | ||
#-- Upload the bitsream to board | ||
#------------------------------ | ||
flash: | ||
iceprog -d i:0x0403:0x6010:0 setbit.bin | ||
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#-- Limpiar todo | ||
clean: | ||
rm -f *.bin *.asc *.json *.out *.vcd *~ | ||
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.PHONY: all clean |
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## Descripción | ||
Componente "hola mundo" con un pin de salida que siempre está a '1'. | ||
Al cargarlo en la Alhambra II se enciende el led D0 | ||
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## Simulación | ||
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Para realizar la simulacion entrar en el directorio y ejecutar: | ||
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`$ make sim` | ||
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Automaticamente se invocará al icarus verilog para hacer la compilacion / simulación y al gtkwave para ver el resultado de la simulacion gráficamente | ||
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## Síntesis | ||
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Para implementar el diseño en la FPGA ejecutamos el comando: | ||
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`$ make sint` | ||
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Se nos genera el fichero setbit.bin que contiene la conguración de la FPGA para que se nos implemente nuestro circuito digital. | ||
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Lo descargamos en la fpga mediante el comando: | ||
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`$ make flash` |
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Bitstreams ya generados listos para cargar en la fpga | ||
(para hacer pruebas sin tener que sintetizar) | ||
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