Fix uncompliant begin in generate blocks #18
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Thanks for all those updates. I added the DCO - can you add the sign-off? I did a cocotb/icarus build and also synthesized the units with Yosys (https://github.com/openpowerwtf/OpenROAD-Tests). |
Signed-off-by: Flavien Solt <flsolt@ethz.ch>
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Thank you for your feedback! I added the signoff. |
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Hi there!
This fixes this Verilog uncompliance issue.
Thanks!
Flavien