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fix decode due to the add of H extension commit Related to 185cac8
Cherry-pick part of (54a6cdd) Zbk: add the Zbk implementation for RV64
Merge conflicts with (185cac8) Add hypervisor extension (chipsalliance#2841)
When all 0, it is 32/64, which can not be represented by log(32)/log(64)
The current Instructions.scala is not up-to-date with riscv-opcodes Previous changes on this file seems to be adding new instructions manually, this can be inferred from riscv/riscv-opcodes@e2ebbf5 which changed the name from parse-opcodes to parse_opcodes thus this PR reorders a lot of instructions and CSRs
As standard instructions are synced from riscv-opcodes
Rocket already implemented NMI in chipsalliance#2711, however, riscv-opcodes currently does not have NMI as it is a WIP (See riscv/riscv-opcodes#67) To avoid generating Instructions.scala from a patched riscv-opcodes, putting NMI related insts/CSRs into CustomInstructions is reasonable.
Better area
ZenithalHourlyRate
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Type of change: bug report | feature request | other enhancement
Impact: no functional change | API addition (no impact on existing code) | API modification
Development Phase: proposal | implementation
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