Use HuanCun instead of block-inclusive-cache (#1016)

* misc: add submodule huancun

* huancun: integrate huancun to SoC as L3

* remove l2prefetcher

* update huancun

* Bump HuanCun

* Use HuanCun instead old L2/L3

* bump huancun

* bump huancun

* Set L3NBanks to 4

* Update rocketchip

* Bump huancun

* Bump HuanCun

* Optimize debug configs

* Configs: fix L3 bug

* Add TLLogger

* TLLogger: fix release ack address

* Support write prefix into database

* Recoding more tilelink info

* Add a database output format converter

* missqueue: add difftest port for memory difftest during refill

* misc: bump difftest

* misc: bump difftest & huancun

* missqueue: do not check refill data when get Grant

* Add directory debug tool

* config: increase client dir size for non-inclusive cache

* Bump difftest and huancun

* Update l2/l3 cache configs

* Remove deprecated fpga/*

* Remove cache test

* Remove L2 preftecher

* bump huancun

* Params: turn on l2 prefetch by default

* misc: remove duplicate chisel-tester2

* misc: remove sifive inclusive cache

* bump difftest

* bump huancun

* config: use 4MB L3 cache

* bump huancun

* bump difftest

* bump difftest

Co-authored-by: wangkaifan <wangkaifan@ict.ac.cn>
Co-authored-by: TangDan <tangdan@ict.ac.cn>

.gitmodules

@@ -1,15 +1,12 @@
 [submodule "rocket-chip"]
 	path = rocket-chip
 	url = https://github.com/OpenXiangShan/rocket-chip.git
-[submodule "block-inclusivecache-sifive"]
-	path = block-inclusivecache-sifive
-	url = https://github.com/OpenXiangShan/block-inclusivecache-sifive.git
 [submodule "chiseltest"]
 	path = chiseltest
 	url = https://github.com/ucb-bar/chisel-testers2.git
 [submodule "api-config-chipsalliance"]
 	path = api-config-chipsalliance
-	url = https://github.com/chipsalliance/api-config-chipsalliance
+	url = https://github.com/chipsalliance/api-config-chipsalliance.git
 [submodule "berkeley-hardfloat"]
 	path = berkeley-hardfloat
 	url = https://github.com/OpenXiangShan/berkeley-hardfloat.git
@@ -19,6 +16,9 @@
 [submodule "ready-to-run"]
 	path = ready-to-run
 	url = https://github.com/OpenXiangShan/ready-to-run
+[submodule "huancun"]
+	path = huancun
+	url = https://github.com/OpenXiangshan/huancun.git
 [submodule "fudian"]
 	path = fudian
 	url = https://github.com/OpenXiangShan/fudian.git

build.sc

@@ -66,12 +66,15 @@ object `rocket-chip` extends SbtModule with CommonModule {
 
 }
 
-object `block-inclusivecache-sifive` extends CommonModule {
+object huancun extends SbtModule with CommonModule {
+
   override def ivyDeps = super.ivyDeps() ++ chisel
 
-  override def millSourcePath = super.millSourcePath / 'design / 'craft / 'inclusivecache
+  override def millSourcePath = super.millSourcePath
 
-  override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`)
+  override def moduleDeps = super.moduleDeps ++ Seq(
+    `rocket-chip`
+  )
 }
 
 object chiseltest extends CommonModule with SbtModule {
@@ -103,9 +106,9 @@ object XiangShan extends CommonModule with SbtModule {
   override def ivyDeps = super.ivyDeps() ++ chisel
   override def moduleDeps = super.moduleDeps ++ Seq(
     `rocket-chip`,
-    `block-inclusivecache-sifive`,
     chiseltest,
     difftest,
+    huancun,
     fudian
   )