IFU: fix the bug of postponing MMIO instruction fetch strategy (#3038)

Co-authored-by: zhou tao <zhoutao@node024.bosccluster.com>
OpenXiangShan · Jun 15, 2024 · ba5ba1d · ba5ba1d
1 parent 6613a2d
commit ba5ba1d
Show file tree

Hide file tree

Showing 2 changed files with 16 additions and 4 deletions.
diff --git a/src/main/scala/xiangshan/frontend/IFU.scala b/src/main/scala/xiangshan/frontend/IFU.scala
@@ -535,7 +535,8 @@ class NewIFU(implicit p: Parameters) extends XSModule
 
   //last instuction finish
   val is_first_instr = RegInit(true.B)
-  io.mmioCommitRead.mmioFtqPtr := RegNext(f3_ftq_req.ftqIdx + 1.U)
+  /*** Determine whether the MMIO instruction is executable based on the previous prediction block ***/
+  io.mmioCommitRead.mmioFtqPtr := RegNext(f3_ftq_req.ftqIdx - 1.U)
 
   val m_idle :: m_waitLastCmt:: m_sendReq :: m_waitResp :: m_sendTLB :: m_tlbResp :: m_sendPMP :: m_resendReq :: m_waitResendResp :: m_waitCommit :: m_commited :: Nil = Enum(11)
   val mmio_state = RegInit(m_idle)
@@ -557,8 +558,14 @@ class NewIFU(implicit p: Parameters) extends XSModule
 
   val f3_need_not_flush = f3_req_is_mmio && fromFtqRedirectReg.valid && !f3_ftq_flush_self && !f3_ftq_flush_by_older
 
-  when(is_first_instr && mmio_commit){
-    is_first_instr := false.B
+  /**
+    **********************************************************************************
+    * We want to defer instruction fetching when encountering MMIO instructions to ensure that the MMIO region is not negatively impacted.
+    * This is the exception when the first instruction is an MMIO instruction.
+    **********************************************************************************
+    */
+  when(is_first_instr && f3_fire){
+    is_first_instr  := false.B
   }
 
   when(f3_flush && !f3_req_is_mmio)                                                 {f3_valid := false.B}

diff --git a/src/main/scala/xiangshan/frontend/NewFtq.scala b/src/main/scala/xiangshan/frontend/NewFtq.scala
@@ -1204,8 +1204,13 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     (isAfter(robCommPtr, commPtr) ||
       PriorityMuxDefault(notInvalidSeq.zip(commitStateQueueReg(commPtr.value).reverse), c_invalid) === c_commited)
 
+  /**
+    *************************************************************************************
+    * MMIO instruction fetch is allowed only if MMIO is the oldest instruction.
+    *************************************************************************************
+    */
   val mmioReadPtr = io.mmioCommitRead.mmioFtqPtr
-  val mmioLastCommit = isBefore(commPtr, mmioReadPtr) && (isAfter(ifuPtr,mmioReadPtr)  ||  mmioReadPtr ===   ifuPtr) &&
+  val mmioLastCommit = (isAfter(commPtr,mmioReadPtr) || (mmioReadPtr === commPtr)) &&
                        Cat(commitStateQueueReg(mmioReadPtr.value).map(s => { s === c_invalid || s === c_commited})).andR
   io.mmioCommitRead.mmioLastCommit := RegNext(mmioLastCommit)