GitHub - PARSA-MHMDI/ALU: In the repository I have implemented a ALU with Finite State machine with VHDL and Xilinx ISE 14.7 application. Also a BCD to seven segment have been implemented for input and output digits.

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In the repository I have implemented a ALU with Finite State machine with VHDL and Xilinx ISE 14.7 application. Also a BCD to seven segment have been implemented for input and output digits.

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Name		Name	Last commit message	Last commit date
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ALU		ALU
Report.docx		Report.docx
Report.pdf		Report.pdf
~$port (2).docx		~$port (2).docx
~WRL3659.tmp		~WRL3659.tmp
پروژه_آزمایشگاه_مدار_منطقی.pdf		پروژه_آزمایشگاه_مدار_منطقی.pdf

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In the repository I have implemented a ALU with Finite State machine with VHDL and Xilinx ISE 14.7 application. Also a BCD to seven segment have been implemented for input and output digits.

vhdl alu xilinx-fpga xilinx-ise

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