Merge pull request #18 from yashgupta26/main

Solved Isseue #15

Verilog Codes for Hardware Modelling/4x1.v

@@ -0,0 +1,17 @@
+module m4x1 (x,s,y);
+
+input [3:0] x;
+input [1:0] s;
+output y;
+
+wire w2,w4,w5,w6,w7,w8,w9,w10;
+
+or g5(y,w7,w8,w9,w10);
+and g1(w7,x[0],w2,w4);
+and g2(w8,x[1],w2,s[1]);
+and g3(w9,x[2],s[0],w4);
+and g4(w10,x[3],s[0],s[1]);
+not g7(w2,s[0]);
+not g6(w4,s[1]);
+
+endmodule

Verilog Codes for Hardware Modelling/fsm.v

@@ -0,0 +1,22 @@
+module cyclic_lamp (clock,
+                    light);
+    input clk;
+    output reg [0:2] light;
+    parameter S0  = 0, S1  = 1, S2  = 2;
+    parameter RED = 3’b100, GREEN = 3’b010, YELLOW = 3’b001;
+    reg [0:1] state;
+    always @(posedge clk)
+        case (state)
+            S0: state      <= S1;
+            S1: state      <= S2;
+            S2: state      <= S0;
+            default: state <= S0;
+        endcase
+        always @(state)
+            case (state)
+                S0: light      = RED;
+                S1: light      = GREEN;
+                S2: light      = YELLOW;
+                default: light = RED;
+            endcase
+        endmodule