cs3220 Pipeline Processor

Created by Yaotian Feng and Will Gulian

See this report for pipelining and optimization explanations.

Folder Structure

• rtl/ - Verilog hardware implementation
• verilator/ - Verilator testbench and GTKwave config
• quartus_project/ - Project for Quartus Prime 18.0 to synthesize the processor.
• test_code/ - mif files to be included into the Quartus Prime build
• docs/ - Miscellaneous documentation