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Merge branch 'smem_kernel_sync'
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@Peque
Peque committed Sep 20, 2012
2 parents b5700a1 + 2f29681 commit 368f1c6
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Showing 12 changed files with 1,222 additions and 1,114 deletions.
26 changes: 9 additions & 17 deletions hw/pcores/master_v1_00_a/data/master_v2_1_0.mpd
View file
Expand Up @@ -50,7 +50,7 @@ PORT address_in_2 = "", DIR = I, VEC = [31:0]
PORT address_in_3 = "", DIR = I, VEC = [31:0]
PORT go = "", DIR = I
PORT ready = "", DIR = O
PORT DEBUG_signal_master = "", DIR = O, VEC = [250:0]
PORT chipscope_probe = "", DIR = O, VEC = [255:0]
PORT DO_0 = "", DIR = O, VEC = [31:0]
PORT DO_1 = "", DIR = O, VEC = [31:0]
PORT DO_2 = "", DIR = O, VEC = [31:0]
Expand All @@ -59,25 +59,17 @@ PORT DI_0 = "", DIR = I, VEC = [31:0]
PORT DI_1 = "", DIR = I, VEC = [31:0]
PORT DI_2 = "", DIR = I, VEC = [31:0]
PORT DI_3 = "", DIR = I, VEC = [31:0]
PORT ADDR_0 = "", DIR = I, VEC = [9:0]
PORT ADDR_1 = "", DIR = I, VEC = [9:0]
PORT ADDR_2 = "", DIR = I, VEC = [9:0]
PORT ADDR_3 = "", DIR = I, VEC = [9:0]
PORT ADDR_0_W = "", DIR = I, VEC = [9:0]
PORT ADDR_1_W = "", DIR = I, VEC = [9:0]
PORT ADDR_2_W = "", DIR = I, VEC = [9:0]
PORT ADDR_3_W = "", DIR = I, VEC = [9:0]
PORT ADDR_0_R = "", DIR = I, VEC = [9:0]
PORT ADDR_1_R = "", DIR = I, VEC = [9:0]
PORT ADDR_2_R = "", DIR = I, VEC = [9:0]
PORT ADDR_3_R = "", DIR = I, VEC = [9:0]
PORT BRAM_CLK = "", DIR = I
PORT TRIG_CLK = "", DIR = I
PORT RST = "", DIR = I
PORT WE_0 = "", DIR = I, VEC = [3:0]
PORT WE_1 = "", DIR = I, VEC = [3:0]
PORT WE_2 = "", DIR = I, VEC = [3:0]
PORT WE_3 = "", DIR = I, VEC = [3:0]
PORT REQ_0 = "", DIR = I
PORT REQ_1 = "", DIR = I
PORT REQ_2 = "", DIR = I
PORT REQ_3 = "", DIR = I
PORT RDY_0 = "", DIR = O
PORT RDY_1 = "", DIR = O
PORT RDY_2 = "", DIR = O
PORT RDY_3 = "", DIR = O

PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
Expand Down
101 changes: 22 additions & 79 deletions hw/pcores/master_v1_00_a/hdl/vhdl/master.vhd
View file
Expand Up @@ -185,20 +185,18 @@ entity master is
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
address_in_0 : in std_logic_vector(31 downto 0);
address_in_1 : in std_logic_vector(31 downto 0);
address_in_2 : in std_logic_vector(31 downto 0);
address_in_3 : in std_logic_vector(31 downto 0);
go : in std_logic;
ready : out std_logic;
DEBUG_signal_master : out std_logic_vector(250 downto 0);
DO_0, DO_1, DO_2, DO_3 : out std_logic_vector(31 downto 0);
DI_0, DI_1, DI_2, DI_3 : in std_logic_vector(31 downto 0);
ADDR_0, ADDR_1, ADDR_2, ADDR_3 : in std_logic_vector(9 downto 0);
BRAM_CLK, TRIG_CLK, RST : in std_logic;
WE_0, WE_1, WE_2, WE_3 : in std_logic_vector(3 downto 0);
REQ_0, REQ_1, REQ_2, REQ_3 : in std_logic;
RDY_0, RDY_1, RDY_2, RDY_3 : out std_logic;
address_in_0 : in std_logic_vector(31 downto 0);
address_in_1 : in std_logic_vector(31 downto 0);
address_in_2 : in std_logic_vector(31 downto 0);
address_in_3 : in std_logic_vector(31 downto 0);
go : in std_logic;
ready : out std_logic;
chipscope_probe : out std_logic_vector(255 downto 0);
DO_0, DO_1, DO_2, DO_3 : out std_logic_vector(31 downto 0);
DI_0, DI_1, DI_2, DI_3 : in std_logic_vector(31 downto 0);
ADDR_0_W, ADDR_1_W, ADDR_2_W, ADDR_3_W : in std_logic_vector(9 downto 0);
ADDR_0_R, ADDR_1_R, ADDR_2_R, ADDR_3_R : in std_logic_vector(9 downto 0);
BRAM_CLK, TRIG_CLK, RST : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
Expand Down Expand Up @@ -378,55 +376,8 @@ architecture IMP of master is
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
-- ------------------
-- signal DEBUG_signal : std_logic_vector(153 downto 0);
-- signal DEBUG_md_error : std_logic;
-- signal DEBUG_m_axi_awvalid : std_logic;
-- signal DEBUG_m_axi_awaddr : std_logic_vector(31 downto 0);
-- signal DEBUG_m_axi_awlen : std_logic_vector(7 downto 0);
-- signal DEBUG_m_axi_awsize : std_logic_vector(2 downto 0);
-- signal DEBUG_m_axi_awburst : std_logic_vector(1 downto 0);
-- signal DEBUG_m_axi_awprot : std_logic_vector(2 downto 0);
-- signal DEBUG_m_axi_wvalid : std_logic;
-- signal DEBUG_m_axi_wdata : std_logic_vector(31 downto 0);
-- signal DEBUG_m_axi_wstrb : std_logic_vector(3 downto 0);
-- signal DEBUG_m_axi_wlast : std_logic;
-- signal DEBUG_m_axi_bready : std_logic;
-- ------------------

begin
-- ------------------ debug
-- md_error <= DEBUG_md_error;
-- m_axi_awvalid <= DEBUG_m_axi_awvalid;
-- m_axi_awaddr <= DEBUG_m_axi_awaddr;
-- m_axi_awlen <= DEBUG_m_axi_awlen;
-- m_axi_awsize <= DEBUG_m_axi_awsize;
-- m_axi_awburst <= DEBUG_m_axi_awburst;
-- m_axi_awprot <= DEBUG_m_axi_awprot;
-- m_axi_wvalid <= DEBUG_m_axi_wvalid;
-- m_axi_wdata <= DEBUG_m_axi_wdata;
-- m_axi_wstrb <= DEBUG_m_axi_wstrb;
-- m_axi_wlast <= DEBUG_m_axi_wlast;
-- m_axi_bready <= DEBUG_m_axi_bready;
-- DEBUG_signal_master <= DEBUG_md_error& --1
-- m_axi_awready& --1
-- DEBUG_m_axi_awvalid& --1
-- DEBUG_m_axi_awaddr& --32
-- DEBUG_m_axi_awlen& --8
-- DEBUG_m_axi_awsize& --3
-- DEBUG_m_axi_awburst& --2
-- DEBUG_m_axi_awprot& --3
-- DEBUG_m_axi_wvalid& --1
-- m_axi_wready& --1
-- DEBUG_m_axi_wdata& --32
-- DEBUG_m_axi_wstrb& --4
-- DEBUG_m_axi_wlast& --1
-- DEBUG_m_axi_bready& --1
-- m_axi_bvalid& --1
-- m_axi_bresp& --2
-- DEBUG_signal; --251
-- --------------
-- --251 bits
-- ------------------
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
Expand Down Expand Up @@ -583,7 +534,7 @@ begin
address_in_3 => address_in_3,
go => go,
ready => ready,
DEBUG_signal => DEBUG_signal_master,
chipscope_probe => chipscope_probe,
DO_0 => DO_0,
DO_1 => DO_1,
DO_2 => DO_2,
Expand All @@ -592,25 +543,17 @@ begin
DI_1 => DI_1,
DI_2 => DI_2,
DI_3 => DI_3,
ADDR_0 => ADDR_0,
ADDR_1 => ADDR_1,
ADDR_2 => ADDR_2,
ADDR_3 => ADDR_3,
ADDR_0_W => ADDR_0_W,
ADDR_1_W => ADDR_1_W,
ADDR_2_W => ADDR_2_W,
ADDR_3_W => ADDR_3_W,
ADDR_0_R => ADDR_0_R,
ADDR_1_R => ADDR_1_R,
ADDR_2_R => ADDR_2_R,
ADDR_3_R => ADDR_3_R,
BRAM_CLK => BRAM_CLK,
TRIG_CLK => TRIG_CLK,
RST => RST,
WE_0 => WE_0,
WE_1 => WE_1,
WE_2 => WE_2,
WE_3 => WE_3,
REQ_0 => REQ_0,
REQ_1 => REQ_1,
REQ_2 => REQ_2,
REQ_3 => REQ_3,
RDY_0 => RDY_0,
RDY_1 => RDY_1,
RDY_2 => RDY_2,
RDY_3 => RDY_3,
-- MAP USER PORTS ABOVE THIS LINE ------------------

Bus2IP_Clk => ipif_Bus2IP_Clk,
Expand Down

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