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PulseRain Rattlesnake - RISCV RV32IMC Soft CPU
Verilog SystemVerilog Python C++ Other
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build/par support mul/div Aug 3, 2019
cores/PLL initial checkin Aug 3, 2019
scripts initial checkin Aug 3, 2019
sim fix compiling error in verilator testbench Aug 3, 2019
source/Intel/cyc10 initial checkin Aug 3, 2019
submodules support mul/div Aug 3, 2019
testbench initial checkin Aug 3, 2019
LICENSE Initial commit Jul 28, 2019
README.md Create README.md Jul 28, 2019

README.md

Rattlesnake

PulseRain Rattlesnake - RISCV RV32IMC Soft CPU

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