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Allow less efficient use of BRAM resources #34

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merged 1 commit into from Oct 12, 2020

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olofk
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@olofk olofk commented Oct 11, 2020

Before this change, yosys required 4096 bits (or at least 50%)
of the bits in a RAM to be used, in order to implement it as a
PB-RAM. Since there are less than 1000 FFs available in the FPGA
it means that any memory using somewhere between 1k and 4k bits
will not fit in the device.

This lowers the requirements on RAM efficiency to be more in line
with the iCE40 backend, which uses comparably sized FPGAs

Signed-off-by: Olof Kindgren olof.kindgren@gmail.com

Before this change, yosys required 4096 bits (or at least 50%)
of the bits in a RAM to be used, in order to implement it as a
PB-RAM. Since there are less than 1000 FFs available in the FPGA
it means that any memory using somewhere between 1k and 4k bits
will not fit in the device.

This lowers the requirements on RAM efficiency to be more in line
with the iCE40 backend, which uses comparably sized FPGAs

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
@olofk olofk requested a review from kgugala as a code owner October 11, 2020 19:46
@tpagarani
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@olofk. This change makes sense. Approving it.

@tpagarani tpagarani merged commit 8d94d13 into QuickLogic-Corp:quicklogic-rebased Oct 12, 2020
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2 participants